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| data sheet, v1.0, february 2010 smartlewis tm rx+ TDA5235 enhanced sensitivity double-configuration receiver with digital baseband processing wireless control never stop thinking.
edition february 19, 2010 published by infineon technologies ag, am campeon 1 - 12 85579 neubiberg, germany ? infineon technologies ag february 19, 2010. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or the infineon technologies companies and our infineon technologies representatives worldwide ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your near est infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system . life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. data sheet, v1.0, february 2010 smartlewis tm rx+ TDA5235 enhanced sensitivity double-configuration receiver with digital baseband processing wireless control never stop thinking. TDA5235 revision number: 010 revision history: 2010-02-19 v1.0 previous version: TDA5235_v0.1 page subjects (major changes since last revision) page 25 update of figure 9 page 27 update of figure 10 page 29 afc limitation added page 31 agc setting proposal added page 32 new section 2.4.6.5 adc added page 34 additional information on rssiprx register inserted page 39 signal and noise detector procedure adapted page 43 x_cdrri register recommendation changed page 47, 50, 54 data slicer modes adapted; limitation added page 67 update of figure 41 page 68 update of figure 42 page 76 additional hint on clock and data recovery algorithm of the user software inserted page 82 pldlen limitation added page 84 limitation for isx readout and burst-read function added page 86 limitation for burst-read function added page 105 description of ?parallel wake-up search? adapted page 123 additional hints added page 125 adaption of section 4.1 page 128 new item c7 added page 136 f comments added for items i6, i7, i8, i9, j11, j12 page 136 item j1 updated page 139 ff general test conditions noted for parameters k, l and m page 145 bom components c7, c8, l1, r2 and r3 updated we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: wirelesscontrol@infineon.com TDA5235 table of contents page data sheet 5 v1.0, 2010-02-19 1 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 pin definition and pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4 functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.1 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.2 block overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4.3 rf/if receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4.4 crystal oscillator and clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4.5 sigma-delta fractional-n pll block . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.5.1 pll dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.4.5.2 digital modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.4.6 ask and fsk demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4.6.1 ask demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4.6.2 fsk demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.4.6.3 automatic frequency control unit (afc) . . . . . . . . . . . . . . . . . . . . . 28 2.4.6.4 digital automatic gain control unit (agc) . . . . . . . . . . . . . . . . . . . . 30 2.4.6.5 analog to digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.7 rssi peak detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4.8 digital baseband (dbb) receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.4.8.1 data filter and signal detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.4.8.2 encoding modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.4.8.3 clock and data recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.4.8.4 data slicer and line decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.4.8.5 wake-up generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.4.8.6 frame synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.4.8.7 message id scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.4.8.8 runin, synchronization search time and inter-frame time . . . . . . 66 2.4.9 power supply circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.4.9.1 supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.4.9.2 chip reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.5 system interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.5.1 interfacing to the TDA5235 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.5.1.1 control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 2.5.1.2 data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.5.2 receive fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.5.3 digital output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 2.5.4 interrupt generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 TDA5235 table of contents page data sheet 6 v1.0, 2010-02-19 2.5.5 digital control (4-wire spi bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 2.5.5.1 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 2.5.6 chip serial number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 2.6 system management unit (smu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 2.6.1 master control unit (mcu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 2.6.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 2.6.1.2 run mode slave (rms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 2.6.1.3 hold mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 2.6.1.4 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 2.6.1.5 self polling mode (spm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 2.6.1.6 automatic modulation switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 2.6.1.7 multi-channel in self polling mode . . . . . . . . . . . . . . . . . . . . . . . . . 104 2.6.1.8 run mode self polling (rmsp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 2.6.2 polling timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 2.6.2.1 self polling modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 2.6.2.2 constant on-off time (coo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 2.6.2.3 fast fall back to sleep (ffb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 2.6.2.4 mixed mode (mm, const on-off & fast fall back to sleep) . . . . . 120 2.6.2.5 permanent wake-up search (pwus) . . . . . . . . . . . . . . . . . . . . . . . 121 2.6.2.6 active idle period selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 2.7 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 2.7.1 definition of bit rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 2.7.2 definition of manchester duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 123 2.7.3 definition of power level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 2.7.4 symbols of sfr registers and control bits . . . . . . . . . . . . . . . . . . . . 126 2.8 digital control (sfr registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 2.8.1 sfr address paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 2.8.2 sfr register list and detailed sfr description . . . . . . . . . . . . . . . . 127 3applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 3.1 configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 4 reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.1 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.1.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4.1.3 ac/dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 4.2 test circuit - evaluation board v1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 4.3 test board layout, evaluation board v1.0 . . . . . . . . . . . . . . . . . . . . . . . 155 4.4 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 appendix - registers chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 data sheet 7 v1.0, 2010-02-19 TDA5235 product description 1 product description 1.1 overview the ic is a low power ask/fsk receiver for the frequency bands 300-320, 425-450, 863-870 and 902-928 mhz. bi-phase modulation schemes, like manchester, bi-phase mark, bi-phase space and differential manchester are supported. the chip offers best-in-class sensitivity performance at a very high level of integration and needs only a few external components. the device is qualified to automotive quality standards and operates between -40 and +105c at supply voltage ranges of 3.0-3.6 volts or 4.5-5.5 volts. the receiver is realized as a double down conversion super-heterodyne/low-if architecture each with image rejection supplemented by digital signal processing in the baseband. a fully integrated sigma-delta fractional-n pll synthesizer allows for high- resolution frequency generation and uses a crystal oscillator as the reference. the on- chip temperature sensor may be utilized for temperature drift compensation via the crystal oscillator. the digital baseband processing unit together with the high performance down converter is the key element for the exceptional sensitivity performance of the device which take it close to the theoretical top-performance limits. it comprises signal and noise detectors, matched data filter, clock and data recovery, data slicer and a format decoder. it demodulates the received ask or fsk data stream independently and recovers the data clock out of the received data stream with very fast synchronization times which can then be either accessed via separate pins or used for further processing like frame synchronization and intermediate storage in the on-chip fifo. the rssi output signal is converted to the digital domain with an adc. all these signals are accessible via the 4- wire spi interface bus. up to 2 pre-configured telegram formats can be stored into the device offering independent pre-processing of the received data to an extent not available till now. the down converter can be also configured in single-conversion mode at moderately reduced selectivity performance but at the advantage of omitting the if ceramic filter. TDA5235 product description data sheet 8 v1.0, 2010-02-19 1.2 features ? enhanced sensitivity receiver ? multi-band (300-320, 425-450, 863-870 and 902-928 mhz) ? one crystal frequency for all supported frequency bands ? 21-bit sigma-delta fractional-n pll synthesizer with high resolution of 10.5 hz ? up to 2 parallel parameter sets for autonomous scanning and receiving from different sources reduces significantly host processor power consumption and system standby power consumption ? one frequency channels per parameter set is supported with 10.5 hz resolution ? autonomous receive mode leads to reduced noise of host processor and improved system performance ? ultrafast wake-up on rssi ? fast synchronization on incoming data stream typically within first 4 bits of a telegram ? selectable if filter bandwidth and optional external filters possible ? double down conversion image reject mixer ? ask and fsk capability ? automatic frequency control (afc) for carrier frequency offset compensation ? supports bi-phase line codes like manchester, bi-phase mark/space and differential manchester ? nrz data pre-processing capability ? digital base band receiver with clock synch, frame synch, format decoding and fifo ? separate outputs for recovered data and clock ? rssi peak detectors ? wake-up generator and polling timer unit ? message id scanning ? unique 32-bit serial number ? on-chip temperature sensor ? integrated timer usable for external watch unit ? integrated 4-wire spi interface bus ? supply voltage range 3.0 volts to 3.6 volts or 4.5 volts to 5.5 volts ? operating temperature range -40 to +105c ? esd protection +/- 2 kv on all pins ? package pg-tssop-28 1.3 applications ? remote keyless entry systems ? remote start applications ? tire pressure monitoring ? short range radio data transmission ? remote control units ? cordless alarm systems ? remote metering data sheet 9 v1.0, 2010-02-19 TDA5235 functional description 2 functional description 2.1 pin configuration figure 1 pin-out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ifbuf_in ifbuf_out gnda ifmix _inp ifmix _inn vdd5v vddd vddd1v5 gndd pp0 pp1 pp2 p_on xtal1 if _out vdda rssi pp3 gndrf lna_inp lna_inn t2 t1 sdo sdi sck ncs xtal2 TDA5235 TDA5235 functional description data sheet 10 v1.0, 2010-02-19 2.2 pin definition and pin functionality table 1 pin definition and function pin no. pad name equivalent i/o schematic function 1 ifbuf_in analog input if buffer input note: input is biased at vdda/2 2 ifbuf_out analog output if buffer output 3 gnda analog ground 4 ifmix_inp analog input + if mixer input note: input is biased at vdda/2 5 ifmix_inn see schematic of pin 1 and 4 analog input. - if mixer input 6 vdd5v analog input 5 volt supply input ifbuf_in ifmix_inn vdda 330 330 ifbuf mix2buf vdda vdda ifbuf_out gnda vdda vdda gnda 330 ifbuf ifmix _inp vdda 330 ifmix_inn mix2buf vdda data sheet 11 v1.0, 2010-02-19 TDA5235 functional description 7 vddd analog input digital supply input 8 vddd1v5 analog output 1.5 volt voltage regulator 9 gndd digital ground 10 pp0 digital output clk_out, rx_run, nint, low, high, data, data_matchfil, ch_data, ch_str, rxd and rxstr are programmable via a sfr (special function register), default = clk_out pin no. pad name equivalent i/o schematic function = + - gndd vddd vdd5v vreg vdd1v5 vddd = + - gndd vreg ppx sdo vdd5v gndd vdd5v gndd TDA5235 functional description data sheet 12 v1.0, 2010-02-19 11 pp1 see schematic of pin 10 digital output clk_out, rx_run, nint, low, high, data, data_matchfil, ch_data, ch_str, rxd and rxstr are programmable via a sfr, default = data 12 pp2 see schematic of pin 10 digital output clk_out, rx_run, nint, low, high, data, data_matchfil, ch_data, ch_str, rxd and rxstr are programmable via a sfr, default = nint 13 p_on digital input power-on reset pin no. pad name equivalent i/o schematic function gndd vdd5v gndd vddd p_on ncs sck sdi data sheet 13 v1.0, 2010-02-19 TDA5235 functional description 14 xtal1 analog input crystal oscillator input 15 xtal2 analog output crystal oscillator output 16 ncs see schematic of pin 13 digital input spi enable 17 sck see schematic of pin 13 digital input spi clock 18 sdi see schematic of pin 13 digital input spi data in 19 sdo see schematic of pin 10 digital output spi data out 20 t1 digital input, connect to digital ground 21 t2 digital input, connect to digital ground pin no. pad name equivalent i/o schematic function xtal1 gndd vddd .... gndd vddd gndd xtal2 gndd vddd .... gndd vddd gndd TDA5235 functional description data sheet 14 v1.0, 2010-02-19 22 lna_inn analog input - rf input 23 lna_inp analog input + rf input 24 gndrf rf analog ground 25 pp3 see schematic of pin 10 digital output rx_run, nint, low, high, data, data_matchfil, ch_data, ch_str, rxd and rxstr are programmable via a sfr, default = rx_run 26 rssi analog output analog rssi output/ analog test pin ana_tst pin no. pad name equivalent i/o schematic function lna_inn gndrf lna lna_inp gndrf lna gnda vdda gnda vdda 500 rssi data sheet 15 v1.0, 2010-02-19 TDA5235 functional description 27 vdda analog input analog supply 28 if_out analog output if output pin no. pad name equivalent i/o schematic function = + - gnda vdda vdd5v vreg if_out ppfbuf vdda vdda gnda 330 gnda TDA5235 functional description data sheet 16 v1.0, 2010-02-19 2.3 functional block diagram figure 2 TDA5235 block diagram 1) 1) the function on each ppx port pin can be programmed via sfr (see also table 1 ). default values are given in squared brackets in figure 2 . vreg 3v3 vreg 3v3 ? pll vreg 1v5 xtal 21.948717 mhz digital demod temp.- sensor signal & noise detectors adc i/f rx fifo pll control i/f rx control i/f ir-mix, 1 st if : 10.7 mhz peripheral bus vddd ir-mix2, 2 nd if: 274.35897 khz peak detectors slicer clock recovery data filter framer spi interface system management 1.5v dig-core 3.3v dig-i/o 3.3v-analog xosc antenna lna ppf ppf buf ppf 2 afc double/single conversion (sdcsel) 1 st if = 10.7 mhz 2 nd if = 1 st if / 39 f cry stal = 2 nd if * 80 lna_inp (23) xtal1 (14) xtal2 (15) lna_inn (22) gndrf (24) gnda (3) vdda (27) vdd5v (6) vddd (7 ) vddd1v5 (8) pp1 (11) [data] p_on (13) t2 (2 1) sdi (18) sdo (1 9) sck (17) ncs (16 ) ifmix_inp (4) ifmix_inn (5) TDA5235 rssi (2 6) t1 (20) ifbuf_in (1) ifbuf_out (2) 10.7 mhz wide 10.7 mhz narrow ( opt ) pp3 (25) [rx_run] narrow wide matching + saw 2nd lo-q 2nd lo-i if_out (28) aaf lp serial number pp2 (1 2) [nint] limiter rssi (cerfsel) clo ck generator pp0 (10) [clk_out] 5v dig-o interrupt generator reset generator gndd (9) to rx to pll clock for digital core reset for digital core adc-mux mux a d 2 nd lo div 2 ifbuf mix2 buf bpf select bw 1st lo-i 1st lo-q data sheet 17 v1.0, 2010-02-19 TDA5235 functional description 2.4 functional block description 2.4.1 architecture overview a fully integrated sigma-delta fractional-n pll synthesizer covers the frequency bands 300-320 mhz, 425-450 mhz, 863-870 mhz, 902-928 mhz with a high frequency resolution, using only one vco running at around 3.6 ghz. for multi-configuration applications requiring different rf channels a very good channel separation is essential. to achieve the necessary high sensitivity and selectivity a double down conversion super-heterodyne architecture is used. the first if frequency is located around 10.7 mhz and the second if frequency around 274 khz. for both if frequencies an adjustment-free image frequency rejection feature is realized. in the second if domain the filtering is done with an on-chip third order bandpass polyphase filter. a multi- stage bandpass limiter completes the rf/if path of the receiver. for single-channel applications with relaxed requirements to selectivity, a single down conversion low-if scheme can be selected. for multi-configuration systems requiring different rf channels where even higher channel separation is required, up to two (switchable) external ceramic (cer) filters can be used to improve the selectivity. an rssi generator delivers a dc signal proportional to the applied input power and is also used as an ask demodulator. via an anti-aliasing filter this signal feeds an adc with 10 bits resolution. the harmonic suppressed limiter output signal feeds a digital fsk demodulator. this block demodulates the fsk data and delivers an afc signal which controls the divider factor of the pll synthesizer. a digital receiver, which comprises rssi peak detectors, a matched data filter, a clock and data recovery, a data slicer, a frame synchronization and a data fifo, decodes the received ask or fsk data stream. the recovered data and clock signals are accessible via 2 separate pins. the fifo data buffer is accessible via the spi bus interface. the crystal oscillator serves as the reference frequency for the pll phase detector, the clock signal of the sigma-delta modulator and divided by two as the 2 nd local oscillator signal. to accelerate the start up time of the crystal oscillator two modes are selectable: a low power mode (with lower precision) and a high precision mode. TDA5235 functional description data sheet 18 v1.0, 2010-02-19 2.4.2 block overview the TDA5235 is separated into the following main blocks: ? rf / if receiver ? crystal oscillator and clock divider ? sigma-delta fractional-n pll synthesizer ? ask / fsk demodulator incl. afc, agc and adc ? rssi peak detector ? digital baseband receiver ? power supply circuitry ? system interface ? system management unit 2.4.3 rf/if receiver the receiver path uses a double down conversion super-heterodyne/low-if architecture, where the first if frequency is located around 10.7 mhz and the second if frequency around 274 khz. for the first if frequency an adjustment-free image frequency rejection is realized by means of two low-side injected i/q-mixers followed by a second order passive polyphase filter centered at 10.7 mhz (ppf). the i/q-oscillator signals for the first down conversion are delivered from the pll synthesizer. the frequency selection in the first if domain is done by an external cer filter (optionally by two, decoupled by a buffer amplifier). for moderate or low cost applications, this ceramic filter can be substituted by a simple lc pi-filter or completely by-passed using the receiver as a single down conversion low-if scheme with 274 khz if frequency. the down conversion to the second if frequency is done by means of two high-side injected i/q-mixers together with an on-chip third order bandpass polyphase filter (ppf2 + bpf). the i/q- oscillator signals for the second down conversion are directly derived by division of two from the crystal oscillator frequency. the bandwidth of the bandpass filter (bpf) can be selected from 50 khz to 300 khz in 5 steps. for a frequency offset of -150 khz to -120 khz, the afc (automatic frequency control) function is mandatory. activated afc option might require a longer preamble sequence in the receive data stream. the receiver enable signal (rx_run) can be offered at each of the port pins to control external components. whenever the receiver is active, the rx_run output signal is active. active high or active low is configurable via ppcfg2 register. data sheet 19 v1.0, 2010-02-19 TDA5235 functional description the frequency relations are calculated with the following formulas: figure 3 block diagram rf section the front end of the receiver comprises an lna, an image reject mixer and a digitally gain controlled buffer amplifier. this buffer amplifier allows the production spread of the on-chip signal strip, of external matching circuitry and rf saw and ceramic if filters to be trimmed. the second image reject mixer down converts the first if to the second if. f if1 10.7mhz = f if2 f if1 39 -------- - = f crystal f if2 80 = f lo2 f crystal 2 ---------------- = f lo1 f crystal nf divider = 2nd order ppf 10.7 mhz ppfbuf cer- filter if1 10 .7 mh z cer- filter if1 10.7 mhz optional cerfsel-mux i- mix2 3rd order bp /pp f2 if2 = 274 khz digital fsk demod multi modulos divider : n_fn lna i-mix q-mix ifbuf q- mix2 limite r rssi generator iq :2 ask / rssi adc rx fsk data rx ask data divider : n afc filter ? modulator crystal oscil - lator pd loop filter iq divider : 4 :1/:2/:3 vco n channel select if attenuation adjust band select lf select channel filter bandwidth select front end control unit band select channel select channel filter select if attenuation adjust lf select rssi gain/ offset adjust rx input mux sdcsel-mux mix2buf (var. gain) lp harm sup lp alias sup TDA5235 functional description data sheet 20 v1.0, 2010-02-19 the bandpass filter follows the subsequent formula: therefore asymmetric corner frequencies can be observed. the use of afc results in more symmetry. a multi-stage bandpass limiter at a center frequency of 274 khz completes the receiver chain. the -3db corner frequencies of the bandpass limiter are typically at 75 khz and at 520 khz. an rssi generator delivers a dc signal proportional to the applied input power and is also used as an ask demodulator. via a programmable anti-aliasing filter this signal is converted to the digital domain by means of a 10-bit adc. the limiter output signal is connected to a digital fsk demodulator. the immunity against strong interference frequencies (so called blockers) is determined by the available filter bandwidth, the filter order and the 3 rd order intercept point of the front end stages. for single-channel applications with moderate requirements to the selectivity the performance of the on-chip 3 rd order bandpass polyphase filter might be sufficient. in this case no external filters are necessary and a single down conversion architecture can be used, which converts the input signal frequency directly to the 2 nd if frequency of 274 khz. figure 4 single down conversion (sdc, no external filters required) for multi-configuration applications requiring different rf channels or systems which demand higher selectivity the double down conversion scheme together with one or two external cer filters can be selected. the order of such ceramic filters is in a range of 3, so the selectivity is further improved and a better channel separation is guaranteed. f center f corner low , f corner high , = 2nd order ppf 10.7 mh z ppfbuf c erfsel-m ux i- mix2 3rd order bp /pp f2 if2 = 274 kh z digital fsk demod lna i-mix q-mix ifb u f q- mix2 lim ite r rssi generator ask / rssi adc rx fsk data rx ask data divider : n if attenuation adjust channel filter bandwidth select rx input mux sdcsel-mux 1 st lo 2 nd lo mix2buf (var. gain) lp harm sup lp alias sup data sheet 21 v1.0, 2010-02-19 TDA5235 functional description figure 5 double down conversion (ddc) with one external filter for applications which demand very high selectivity and/or channel separation even two cer filters may be used. also in applications where one configuration/channel requires a wider bandwidth than the other (e.g. tpms and rke) the second filter can be by- passed. figure 6 double down conversion (ddc) with two external filters 2nd order ppf 1 0.7 m h z ppfbuf cer- filter if1 10 .7 mhz cerfsel-mux i- mix2 3rd order bp /pp f2 if2 = 274 kh z digital fsk demod lna i-mix q-mix ifb u f q- mix2 lim ite r rssi generator ask / rssi adc rx fsk data rx ask data divider : n if attenuation adjust channel filter bandwidth select rx input mux sdcsel-mux 1 st lo 2 nd lo m ix2buf (var. gain) lp harm sup lp alias sup 2nd order ppf 10.7 mhz ppfbuf cer- filter if1 10 .7 mhz cer- filter if1 10.7 mhz optional cerfsel-mux i- mix2 3rd order bp /pp f2 if2 = 274 kh z digital fsk demod lna i-mix q-mix ifb u f q- mix2 lim ite r rssi generator ask / rssi adc rx fsk data rx ask data divider : n if attenuation adjust channel filter bandwidth select rx input mux sdcsel-mux 1 st lo 2 nd lo mix2buf (var. gain) lp harm sup lp alias sup TDA5235 functional description data sheet 22 v1.0, 2010-02-19 2.4.4 crystal oscillator and clock divider the crystal oscillator is a pierce type oscillator which operates together with the crystal in parallel resonance mode. an automatic amplitude regulation circuitry allows the oscillator to operate with minimum current consumption. in sleep mode, where the current consumption should be as low as possible, the load capacitor must be small and the frequency is slightly detuned, therefore all internal trim capacitors are disconnected. the internal capacitors are controlled by the crystal oscillator calibration registers xtalcalx. with a binary weighted capacitor array the necessary load capacitor can be selected. whenever a xtalcalx register value is updated, the selected trim capacitors are automatically connected to the crystal so that the frequency is precise at the desired value. the sfr control bit xtalhpms can be used to activate the high precision mode also during sleep mode. figure 7 crystal oscillator xtal2 xtal1 oscillator -core (dgnd) binary weighted capacitor-array binary weighted capacitor-array f sys xtalcal0 setting automatically controlled ( 1pf steps ) xtalhpms xtalcal1 9 data sheet 23 v1.0, 2010-02-19 TDA5235 functional description recommended trimming procedure ? set the registers xtalcal0 and xtalcal1 to the expected nominal values ? set the TDA5235 to run mode slave ? wait for 0.5ms minimum ? trim the oscillator by increasing and decreasing the values of xtalcal0/1 ? register changes larger than 1 pf are automatically handled by the TDA5235 in 1pf steps ? after the oscillator is trimmed, the TDA5235 can be set to sleep mode and keeps these values during sleep mode ? add the settings of xtalcal0/1 to the configuration. it must be set after every power up or brownout! using the high precision mode as discussed earlier, the TDA5235 allows the crystal oscillator to be trimmed by the use of internal trim capacitors. it is also possible to use the trim functionality to compensate temperature drift of crystals. during run mode (always when the receiver is active) the capacitors are automatically connected and the oscillator is working in the high precision mode. on entering sleep mode, th e capacitor s are automatically disconnected to save power. if the high precision mode is also required for sleep mode, the automatic disconnec- tion of trim capacitors can be avoided by setting xtalhpms to 1 (enable xtal high precision mode during sleep mode). external clock generation unit a built in programmable frequency divider can be used to generate an external clock source out of the crystal reference. the 20 bit wide division factor is stored in the registers clkout0, clkout1 and clkout2. the minimum value of the programmable frequency divider is 2. this programmable divider is followed by an additional divider by 2, which generates a 50% duty cycle of the clk_out signal. so the maximum frequency at the clk_out signal is the crystal frequency divided by 4. the minimum clk_out frequency is the crystal frequency divided by 2 21 . to save power, this programmable clock signal can be disabled by the sfr control bit clkouten. in this case the external clock signal is set to low. TDA5235 functional description data sheet 24 v1.0, 2010-02-19 the resulting clk_out frequency can be calculated by: figure 8 external clock generation unit the maximum clk_out frequency is limited by the driver capability of the ppx pin and depends on the external load connected to this pin. please be aware that large loads and/or high clock frequencies at this pin may interfere with the receiver and reduce performance. after reset the ppx pin is activated and the division factor is initialized to 11 (equals f clk_out = 998 khz). a clock output frequency higher than 1 mhz is not supported. for high sensitivity applications, the use of the external clock generation unit is not recommended. f clkout f sys 2 divisionfactor ? -------------------------------------------- - = 20 bit counter divide by 2 f clk_out 2 x f clk_out f sys clkout0 clkout1 clkout2 clkouten enable enable data sheet 25 v1.0, 2010-02-19 TDA5235 functional description 2.4.5 sigma-delta fractional-n pll block the sigma-delta fractional-n pll is fully integrated on chip. the v oltage c ontrolled o scillator (vco) with on-chip lc-tank runs at approximately 3.6 ghz and is first divided with a band select divider by 1, 2 or 3 and then with an i/q-divider by 4 which provides an orthogonal local oscillator signal for the first image reject mixer with the necessary high accuracy. the multi-modulus divider determines the channel selection and is controlled by a 3 rd order sigma-delta modulator ( sdm ). a type iv phase detector, a charge pump with programmable current and an on-chip loop filter closes the phase locked loop. figure 9 synthesizer block diagram qosc 22mhz iq divider 4 multi- modulus divider pfd ? modulator loop filter band select 1/2/3 3.6 ghz vco cp afc filter afc-data to 1 st mixer channel fn TDA5235 functional description data sheet 26 v1.0, 2010-02-19 when defining a multi-configuration system requiring different rf channels, the correct selection of channel spacing is extremely important. a general rule is not possible, but following must be considered: ? if an additional saw filter is used, all channels including their tolerances have to be inside the saw filter bandwidth. ? the distance between channels must be high enough, that no overlapping can occur. strong input signals may still appear as recognizable input signal in the neighboring channel because of the limited suppression of if filters. example: a typical 330khz if filter has at 10.3 mhz ( 10.7 mhz - 0.4 mhz ) only 30 db suppression. a -70 dbm input signal appears like a -100 dbm signal, which is inside the receiver sensitivity. in critical cases the use of two if filters must be considered. see also chapter 2.4.3 rf/if receiver . 2.4.5.1 pll dividers the divider chain consists of a band select divider 1/2/3, an i/q-divider by 4 which provides an orthogonal 1st local oscillator signal for the first image reject mixer with the necessary high accuracy and a multi-modulus divider controlled by the sigma-delta modulator. with the band select divider, the wanted frequency band is selected. divide by 1 selects the 915 mhz and 868 mhz band, divide by 2 selects the 434 mhz band and divide by 3 selects the 315 mhz band. the ism band selection is done via bit group bandsel in x_pllintc1 register. 2.4.5.2 digital modulator the 3 rd order sigma-delta modulator (sdm) has a 22 bit wide input word, however the lsb is always high, and is clocked by the xtal oscillator. this determines the achievable frequency resolution. the automatic frequency control unit filters the actual frequency offset from the fsk demodulator data and calculates the necessary correction of the divider factor to achieve the nominal if center frequency. data sheet 27 v1.0, 2010-02-19 TDA5235 functional description 2.4.6 ask and fsk demodulator figure 10 functional block diagram ask/fsk demodulator the ic comprises two separate demodulators for ask and fsk. after combining fsk and ask data path, a sampling rate adaptation follows to meet an output oversampling between 8 and 16 samples per chip. finally, an oversampling of 8 samples per chip can be achieved using a fractional sample rate converter (src) with linear interpolation (for further details see figure 15 ). 2.4.6.1 ask demodulator the rssi generator delivers a dc signal proportional to the applied input power at a logarithmic scale (dbm) and is also used as an ask demodulator. via a programmable anti-aliasing filter this signal is converted to the digital domain by means of a 10-bit adc. for the am demodulation a signal proportional to the linear power is required. therefore a conversion from logarithmic scale to linear scale is necessary. this is done in the digital domain by a nonlinear filter together with an exponential function. the analog rssi signal after the anti-aliasing filter is available at the rssi pin via a buffer amplifier. to enable this buffer the sfr control bit rssimonen must be set. the anti-aliasing filter can be by-passed for visualization on the rssi pin (see aafbyp control bit). 2nd conversion delog ask fsk b = 50..300khz ppf2 bp rssi adc channel filter fm limiter image suppression / band limitation (noise) fsk demodulator 33 / 46 / 65 / 93 / 132 / 190 / 239 / 282 khz (2sided pdf bw) 8 ? 16 samples /chip (data rate dependent ) fsk/ask rf pll ctrl fsk demodulator afc loop filter div f system demodulated data rssi buffer rssi slope rssi offset peak memory filter rssi peak detector register agc rssipmf register rssipwu (internal signal) > begin of config / channel , x*wulot wu event th, bl, bh bypass rate adapter rate doubler decimation rssipwu register end of config/ channel afc track/freeze dig. gain control analog gain control mux temp vddd/2 TDA5235 functional description data sheet 28 v1.0, 2010-02-19 2.4.6.2 fsk demodulator the limiter output signal, which has a constant amplitude over a wide range of the input signal, feeds the fsk demodulator. there is a configurable lowpass filter in front of the fsk demodulation to suppress the down conversion image and noise/limiter harmonics (fsk pre-demodulation filter, pdf). this is realized as a 3 rd order digital filter. the sampling rate after fsk demodulation is fixed and independent from the target data rate. 2.4.6.3 automatic frequency control unit (afc) in front of the image suppression filter a second fsk demodulator is used to derive the control signal for the automatic frequency control unit , which is actually the dc value of the fsk demodulated signal. this makes the afc loop independent from signal path filtering and allow so a wider frequency capture range of the afc. the derivation of the afc control signal is preferably done during the dc free preamble and is then frozen for the rest of the datagram. since the digital fsk demodulator determines the exact frequency offset between the received input frequency and the programmed input center frequency of the receiver, this offset can be corrected through the sigma delta control of the pll. as shown in figure 10 , for afc purposes a parallel demodulation path is implemented. this path does not contain the digital low pass filter (pdf, pre-demodulation filter). the entire if bandwidth, filtered by the analog bandpass filter only, is processed by the afc demodulator. there are two options for the active time of the afc loop: ? 1. always on ? 2. active for a programmable time relative to a signal identification event (several options can be programmed in sfr). in the latter case the afc can either be started or frozen relative to the signal identification. after the active time the offset for the sigma-delta pll (sd pll) is frozen. the programming of the active time is especially necessary in case the expected frame structure contains a gap (noise) between wake-up and payload in order to avoid the afc from drifting. afc works both for fsk and ask. in the latter case the afc loop only regulates during ask data = high. the maximum frequency offset generated by the afc can be limited by means of the x_afclimit register. this limit can be used to avoid the afc from drifting in the presence of interferers or when no rf input signal is available (afc wander). a maximum afc limit of 42 khz is recommended. afc wandering needs to be kept in mind especially when using run mode slave. data sheet 29 v1.0, 2010-02-19 TDA5235 functional description figure 11 afc loop filter (i-pi filtering and mapping) the bandwidth (and thus settling time) of the loop is programmed by means of the integrator gain coefficients k1 and k2 (x_afck1cfg and x_afck2cfg register). k1 mainly determines the bandwidth. k2 influences the dynamics/damping (overshoot) - smaller k2 means smaller overshoot, but slower dynamics. the bandwidth of the afc loop is approximately 1.3*k1. to avoid residual fm, limiting the afc bw to 1/20 ~ 1/40 of the bit rate is suggested, therefore k1 must be set to approximately 1/50 ~ 1/100 of the bit rate. for most applications k2 can be set equal to k1 (overshoot is then <25%). when very fast settling is necessary k1 and k2 can be increased up to bit rate/10, however, in this case approximately 1db sensitivity loss is to be expected due to the afc counteracting the input fsk signal. afc limitation at local oscillator (lo) frequencies at multiples of reference frequency (f_xtal). when afc is activated and afc drives the wanted lo frequency over the integer limit of sigma delta (sd) modulator, the sd modulator stucks at frac=1.0 or frac=0.0 due to saturation. so when afc can change the integer value for the lo (register x_pllintc1) within the frequency range lo-frequency +/- afc-limit, a change of the lo injection side or a smaller afc-limit is recommended. the frequency offset found by afc (afc loop filter output) can be readout via register afcoffset, when afc is activated. the value is in signed representation and has a frequency resolution of 2.68 khz/digit. the output can be limited by the x_afclimit register. x_afck 1cfg 0/1 afc demod out freqoffset sdpll scaling & limiting hold delay x_afcagcd integrator 1 x_afck 2cfg0/1 x_afclimit k2 = integrator 2 gain k1 = integrator 1 gain k2 x4 + freeze * / track hold limit hold limit integrator 2 k1 x16 TDA5235 functional description data sheet 30 v1.0, 2010-02-19 2.4.6.4 digital automatic gain control unit (agc) automatic gain control (agc) is necessary mainly because of the limited dynamic range of the on-chip bandpass filter (bpf). the dynamic range reduces to less than 60db in case of minimum bpf bandwidth. agc is used to cover the following cases: 1. ask demodulation at large input signals 2. rssi reading at large input signals 3. improve iip3 performance in either fsk or ask mode the 1 st if buffer (ppfbuf, see figure 3 ) can be fine tuned "manually" by means of 4 bits thus optimizing the overall gain to the application (attenuation of 0db to -12db by means of ifatt0 to ifatt15 in ddc mode; sdc mode has lower ifatt range). this buffer allows the production spread of external components to be trimmed. the gain of the 2 nd if path is set to three different values by means of an agc algorithm. depending on whether the receiver is used in single down conversion or in double down conversion mode the gain control in the 2 nd if path is either after the 2 nd poly-phase network or in front of the 2 nd mixer. the agc action is illustrated in the rssi curve below: figure 12 analog rssi output curve with agc action on (blue) vs. off (black) limiter noise floor front-end noise x gain mixer2 saturation input power analog (blue ) & digital (black ) rssi output min. fe gain (ifa tt 15) bpf saturation margin analog agc attack point max. fe gain (ifatt 0) ma x . b w min . b w analog agc decay point hysteresis bpf bypassed agc off agc on ma x . b w min . b w ag ct h of f s agctlo agchys ag ct up ag ch y s data sheet 31 v1.0, 2010-02-19 TDA5235 functional description digital rssi, agc and delog: in order to match the analog rssi signal to the digital rssi output a correction is necessary. it adds an offset (rssioffs) and modifies the slope (rssislope) such that standardized agc levels and an appropriate delog table can be applied. upon entering the agc unit the digital rssi signal is passed through a peak memory filter (pmf). this filter has programmable up and down integration time constants (pmfup, pmfdn) to set attack respectively decay time. the integration time for decay time must be significantly longer than the attack time in order to avoid the agc interfering with the ask modulation. the integrator is followed by two digital schmitt triggers with programmable thresholds (agctlo; agctup) - one schmitt trigger for each of the two attack thresholds (two digital agc switching points). the hysteresis of the schmitt triggers is programmable (agchys) and sets the decay threshold. the schmitt triggers control both the analog gain as well as the corresponding (programmable) digital gain correction (dgc). the difference ("error") signal in the pmf is actually a normalized version of the modulation. this signal is then used as input for the delog table. agc threshold programming the sfr description for the agc thresholds are in dbs. the first value to set is the agc threshold offset in agcthoffs. this value is the offset relative to 0 input (no noise, no signal), which for the default setting of gain, and assuming typical insertion loss of matching network and ceramic filter, can be extrapolated to be approximately -143dbm. in this case the default setting of the agcthoffs of 63.9db corresponds to an input power of approximately -79dbm (= -143dbm + 63.9db). the low (digital) agc threshold is then -79 + 12.8db (default agctlo) = -66dbm and the upper (digital) agc threshold is -79 + 25.6 (default agctup) = -53dbm. therefore a margin of about 6db is indicated before a degradation of the linearity of the 2 nd if can be observed when using the 50khz bpf or even about 16db when using the 300khz bpf. the input power level at which the agc switches back to maximum gain is -66dbm - 21.3db (default agchys) = -87dbm. this provides enough margin against the minimum sensitivity. TDA5235 functional description data sheet 32 v1.0, 2010-02-19 when agc is activated, rssi is untrimmed, ifatt <= 5.6db and the same rssi offset should be applied for all bandpass filter settings, then the settings in table 2 can be applied, where a small reduction of the rssi input range can be observed. for the full rssi input range, the values in table 3 can be applied. table 2 agc settings 1 agc threshold hysteresis = 21.3 db agc digital rssi gain correction = 15.5 db bpf rssi offset compensation (untrimmed) 1) 1) note: this value needs to be used for calculating the register value agc threshold offset agc threshold low agc threshold up rssi input range reduction 300 khz 32 63.9 db 8 4 5 db 200 khz 32 63.9 db 6 2 5 db 125 khz 32 63.9 db 5 0 5 db 80 khz 32 51.1 db 11 6 2.8 db 50 khz 32 51.1 db 9 5 0 db table 3 agc settings 2 agc threshold hysteresis = 21.3 db agc digital rssi gain correction = 15.5 db bpf rssi offset compensation (untrimmed) 1) 1) note: this value needs to be used for calculating the register value agc threshold offset agc threshold low agc threshold up 300 khz -18 63.9 db 5 1 200 khz -18 51.1 db 11 7 125 khz -18 51.1 db 10 5 80 khz 4 51.1 db 9 5 50 khz 32 51.1 db 9 5 data sheet 33 v1.0, 2010-02-19 TDA5235 functional description attack and decay coefficients pmf-up & pmf-down: the settling time of the loop is determined by means of the integrator gain coefficients pmfup and pmfdn, which need to be calculated from the wanted attack and decay times. the adc is running at a fixed sampling frequency of 274khz. therefore the integrator is integrating with pmfup*274k per second, i.e. time constant is 1/(pmfup*274k). the attack times are typically 16 times faster than the decay times. typical calculation of the coefficients by means of an example: ? pmfup = 2^-round( ln(atttime / bitrate * 274khz) / ln(2) ) ? pmfdn = 2^-round( ln(dectime / bitrate * 274khz) / ln(2) ) / pmfup where atttime, dectime = attack, decay time in number of bits note: pmfdn = overall_pmfdn / pmfup example: bitrate = 2kbps atttime = 0.1 bits => pmfup = 2^-round(ln(0.1bit/2kbps*274khz)/ln(2)) = 2^-round(3.8) = 2^-4 dectime = 2 bits => pmfdn = 2^-round(ln(2bit/2kbps*274khz)/ln(2))/pmfup = 2^-round(8.1)/2^-4 = 2^-4 note: in case of ask with large modulation index the attack time (pmfup) can be up to a factor 2 slower due to the fact that the ask signal has a duty cycle of 50% - during the ask low duration the integrator is actually slightly discharged due to the decay set by pmfdn. the agc start and freeze times are programmable. the same conditions can be used as in the corresponding afc section above. they will however, be programmed in separate sfr registers. TDA5235 functional description data sheet 34 v1.0, 2010-02-19 2.4.6.5 analog to digital converter (adc) in front of the ad converter there is a multiplexer so that also temperature and vddd can be measured (see figure 10 ). the default value of the adc-mux is rssi (register adcinsel: 000 for rssi; 001 for temperature; 010 for vddd/2). after switching adc-mux to a value other than rssi in sleep mode, the internal references are activated and this adc start-up lasts 100s. so after this adc start-up time the readout measurements may begin. the chip stays in this mode until reconfiguration of register adcinsel to setting rssi. however, it is recommended to measure temperature during sleep mode (this is also valid for vddd). readout of the 10-bit adc has to be done via adcresh register (the lower 2 bits in adcresl register can be inconsistent and should not be used). typical the adc refresh rate is 3.7 s. time duration between two adc readouts has to be at least 3.7 s, so this is already achieved due to the maximum spi rate (16 bit for spi command and address last 8s at an spi rate of 2mbit/s). the eoc bit (end of conversion) indicates a successful conversion additionally. repetition of the readout measurement for several times is for averaging purpose. the input voltage of the adc is in the range of 1 .. 2 v. therefore vddd/2 (= 1.65 v typical) is used to monitor vddd. further details on the measurement and calibration procedure for temperature and vddd can be taken from the corresponding application note. data sheet 35 v1.0, 2010-02-19 TDA5235 functional description 2.4.7 rssi peak detector the ic possesses several digital rssi peak level detectors. the rssi level is averaged over 4 samples before it is fed to any of the peak detectors. this prevents the evaluated peak values to be dominated by single noise peaks. figure 13 peak detector unit peak detector payload is used to measure the input signal power of a received and accepted data telegram. it is read via sfr rssippl. observation of the rssi signal starts at the detection of a tsi (fsync) and ends with the detection of eom. the internal rssippl value is cleared after fsync. the evaluated rssi peak level rssippl is transferred to the rssippl register at eom. starting the observation of the rssi level can be delayed by a selectable number of data bits and is controlled by the register x_pkbitpos. a latency in the generation of fsync and eom of approx. 2..3 bits in relation to the contents of the peak detector must be considered. within the boundaries described, the register rssippl always contains the peak value of the last completely received data telegram. the register rssippl is reset to 0 at power up reset only. peak detector is used to measure rssi independent of a data transfer and to digitally trim rssi. it is read via sfr rssiprx. observation of the rssi signal is active whenever the rx_run signal is high. the rssiprx register is refreshed and the peak detector is reset after every read access to rssiprx. it may be required to read rssiprx twice to obtain the required result. this is because, for example, during a trim procedure in which the input signal power is reduced, after a d from rssi generator rssi i&d averaging filter adc sampling clock generation f sys divide by 4 integrate dump to ask path f adc f adc /4 peak detector rssiprx read access to register rssiprx from spi controller peak detector payload compare rssippl fsync peak detector track control peak value register update eom update peak value update load compare peak- value load & from fsm rx_run bit position rssi slope rssi offset rssirx TDA5235 functional description data sheet 36 v1.0, 2010-02-19 reading rssiprx, the peak detector will still hold the higher rssi level. after reading rssiprx the lower rssi level is loaded into the peak detector and can be read by reading rssiprx again. register rssiprx should not be read-out faster than 41s in case agc is on (as register value would not represent the actual, but a lower value). when the rx_run signal is inactive, a read access has no influence to the peak detector value. the register rssiprx is reset to 0 at power up reset. peak detector wake-up rssipwu (see figure 10 ) is used to measure the input signal power during wake-up search. the internal signal rssipwu gets initialized to 0 at start of the first observation time window at the beginning of each configuration. the peak value of this signal is tracked during wake-up search. in case of a wake-up, the actual peak value is written in the rssipwu register. even in case no wake-up occurred, actual peak value is written in the rssipwu register at the end of the actual configuration of the self polling period. so if no wake-up occurred, then the rssipwu register contains the peak value of the last configuration of the self polling period, even in a multi-configuration setup. this functionality can be used to track rssi during unsuccessful wake-up search due to no input signal or due to blocking rssi detection. for further details please refer to chapter 2.4.8.5 wake-up generator and chapter 2.6.2 polling timer unit . figure 14 peak detector behavior d0 tsi run-in d1 .... dn .... reset fsync eom internal rssi n = pkbitpos run-in eom fsync input data pattern noise noise dn -1 fsync clears the internal rssippl rssippl register internal rssi internal rssiprx = rssiprx register spi read out rssippl&rssiprx spi internal rssippl dn +1 dn +2 dn +3 *1 *1 *1 *1 computation delay due to filtering and signal calculation. tsi *1 d0 d1 .... data sheet 37 v1.0, 2010-02-19 TDA5235 functional description recommended digital trimming procedure ? download configuration file (run mode slave; rssislope, rssioffs set to default, i.e. rssislope=1, rssioffs=0) ? turn off agc (agcstart=0) and set gain to agcgain=0 ? apply p in1 = -85 dbm rf input signal ? read rssirx eleven times (minimum 10 ms in-between readings), use average of last ten readings (always), store as rssim1 ? apply p in2 = -65 dbm rf input signal ? read rssirx eleven times (minimum 10 ms in-between readings), use average of last ten readings (always), store as rssim2 ? calculate measured rssi slope slopem=(rssim2-rssim1)/(p in2 -p in1 ) ? adjust rssislope for required rssi slope sloper as follows: rssislope=sloper/slopem ? adjust rssioffs for required value rssir2 at p in2 as follows: rssioffs=(rssir2-rssim2)+(slopem-sloper)*p in2 ? the new values for rssislope and rssioffs have to be added to the configuration! notes: 1. the upper rf input level must stay well below the saturation level of the receiver (see chapter 2.4.6.4 digital automatic gain control unit (agc) ) 2. the lower rf input level must stay well above the noise level of the receiver 3. if if attenuation is trimmed, this has to be done before trimming of rssi 4. if rssi needs to be trimmed in a higher input power range the agcgain must be set accordingly TDA5235 functional description data sheet 38 v1.0, 2010-02-19 2.4.8 digital baseband (dbb) receiver figure 15 functional block diagram digital baseband receiver the digital baseband receiver comprises a matched data filter, a clock and data recovery, a data slicer, a line decoder, a wake-up generator, a frame synchronization and a data fifo. the recovered data and clock signals are accessible via 2 separate pins. the fifo data buffer is accessible via the spi bus interface. 2.4.8.1 data filter and signal detection the data filter is a matched filter ( mf ). the frequency response of a matched filter has ideally the same shape as the power spectral density ( psd ) of the originally transmitted signal, therefore the signal-to-noise ratio ( snr ) at the output of the matched filter becomes maximum. the input sampling rate of the baseband receiver has to be between 8 and 16 samples per chip. the oversampling factor within this range is depending on the data rate (see figure 10 ). the mf has to be adjusted accordingly to this oversampling. after the mf a fractional sample rate converter (src) is applied using linear interpolation. depending on the data rate decimation is adjusted within the range 1...2. finally, at the output of the fractional src the sampling rate is adjusted to 8 samples per chip for further processing. to distinguish whether the incoming signal is really a signal or only noise adequate detectors for ask and fsk are built in. eom fsync data data_clk wakeup 8 to 16 samples per chip fsk detector fractional src src bypass fs out / fs in = 0.5 ? 1.0 adjust_length matched filter raw data slicer for external processing data (sliced raw data for external processing ) signal detector chip_data chip _data_clock sync cr pll slicer cdr pll blind sync initial phase & data rate data slicer chip data decoder framer (tsi detector) decoder wu unit from ask/ fsk demodulator rxstr rxd fifo ch_str ch_data mux sign data_matchfil (matched filtered data for external processing ) chip data invert data invert data invert dinvext chipdinv data sheet 39 v1.0, 2010-02-19 TDA5235 functional description signal and noise detector the signal detector decides between acceptable and unacceptable data (e.g. noise). this decision is taken by comparing the signal power of the actually received data (register spwr) with a configurable threshold level (registers x_sigdet0/1), which must be evaluated. in case the actual signal power is above the threshold, acceptable data has been detected. to decide in case of fsk whether there is a data signal or simply noise at the output of the rate adapter, there is a noise detector implemented. the principle is based on a power measurement of the demodulated signal. the current noise power is stored in the npwr register and is updated at every spi controller access. the noise detector is useful if data signal is transmitted with small fsk deviations. in case the current noise power (register npwr) is below the configurable threshold (register x_ndthres), a data signal has been detected. the signal recognition mode must be configured based on whether ask or fsk modulation is used. signal recognition can be a combination of signal detector and noise detector: ? signal detector (=squelch) only (related registers: x_sigdet0, x_sigdet1 and spwr). this mode is generally used for ask and recommended for fsk. ? noise detector only (related registers: x_ndthres and npwr). ? signal and noise detector simultaneously. ? signal and noise detector simultaneously, but the fsk noise detect signal is valid only if the x_sigdetlo threshold is exceeded. this is the recommended fsk mode, if minimum fsk deviation is not sufficient to use signal detector only. signal recognition can also be used as wake-up on level criterion (see chapter 2.4.8.5 ). figure 16 shows the system characteristics to consider in choosing the best signal detector level. on the one hand, a higher sigdet threshold level must be set for achieving good far (false alarm rate) performance, but then the mer/ber (message error rate/bit error rate) performance will decrease. on the other hand, the mer/ber performance can be increased by setting smaller sigdet threshold levels but then the far performance will worsen. TDA5235 functional description data sheet 40 v1.0, 2010-02-19 figure 16 signal detector threshold level quick procedure to determine signal and noise detector thresholds preparation a setup is required with original rf hardware as in the final application. the values of spwr and npwr can be read via the final application. a complete configuration file using right modulation, data rate and run mode slave, must be prepared and downloaded to the TDA5235. signal detector threshold for ask take 500 readings of spwr (50 are also possible, but this leads to less accurate results) with no rf input signal applied (=noise only). calculate average and standard deviation. signal detector threshold is average plus 2 times the standard deviation. to load the x_sigdet0/1 register the calculated value must be rounded and converted to hexadecimals. for a final application, the signal detector threshold should be varied to optimize the false alarm rate and the sensitivity. signal and noise detector thresholds for fsk signal detector threshold do 500 (50) readings of spwr with no rf input signal applied (=noise only). calculate average and standard deviation. signal detector threshold is average plus 2 times the standard deviation. of course this value has to be rounded and converted to telegram better far performance better mer/ber performance high sdthr level low sdthr level signal power input data sdthr level area data sheet 41 v1.0, 2010-02-19 TDA5235 functional description hexadecimals. for a final application the signal detector threshold should be varied to optimize the false alarm rate and the sensitivity. verification if squelch only is possible apply a bit pattern (e.g. prbs9) with correct data rate at about -80 dbm input signal power and minimum fsk deviation to the rf input. do 500 (50) readings of spwr, calculate average minus three times the standard deviation. this value should be higher than the calculated signal detector threshold calculated above. if this is not the case, signal detector and noise detector must be used. noise detector threshold do 500 (50) readings of npwr with no rf input signal applied (=noise only). calculate average and standard deviation. noise detector threshold is average minus the standard deviation. round this value and convert it to hexadecimals. for a final application, the noise detector threshold should be varied to optimize false alarm rate and sensitivity. signal detector low threshold the signal detector low threshold is always required in combination with the noise detector. set register bit sdlore to 1 and set bit group sdlorsel to 00. apply a bit pattern (e.g. prbs9) at correct data rate at about -80 dbm input signal power and minimum fsk deviation to the rf input. do 500 (50) readings of spwr, calculate average. if average is larger than 200 dec (=0xc8), sdlorsel has to be increased to the next larger value until average is smaller than 200 dec. x_sigdetlo = 0.8 * (average - 3 * standard deviation). set register sdlore back to 0. the last setting of bit group sdlorsel must also be used for configuration! verification threshold settings should be verified by testing receiver sensitivity over the input frequency range, with a step size of 100hz, at minimum fsk deviation with all combinations of minimum and maximum data rate and duty cycle. further detailed information can be taken from the corresponding application note. TDA5235 functional description data sheet 42 v1.0, 2010-02-19 2.4.8.2 encoding modes the ic supports the following bi-phase encodings: ? manchester code ? differential manchester code ? bi-phase space code ? bi-phase mark code the encoding mode is set and enabled by bit group code in x_digrxc configuration register. figure 17 coding schemes the encoding modes inverted manchester and inverted differential manchester can also be decoded internally by usage of chipdinv bit in x_digrxc register (see figure 15 ). all the manchester symbol combinations including code violations are shown in figure 18 . digital 0 and 1 are coded with the change of the amplitude in the middle of the symbol period. the code violations (cv) m (mark) and s (space), are coded as low/high signal levels. figure 18 manchester symbols including code violations data clock manchester differential manchester biphase space biphase mark 10100110 0 1 sm 1st chip 2nd chip 1st chip 2nd chip 1st chip 2nd chip 1st chip 2nd chip data sheet 43 v1.0, 2010-02-19 TDA5235 functional description 2.4.8.3 clock and data recovery an all-digital pll ( adpll ) recovers the data clock from the incoming data stream. the second main function is the generation of a signal indicating symbol synchronization. synchronization on the incoming data stream generally occurs within the first 4 bits of a telegram. figure 19 clock recovery (adpll) clock recovery is implemented as standard adpll pi regulator with timing extrapolation unit for fast settling. in the unlocked state, the timing extrapolation unit calculates the frequency offset for the incoming data stream. if the defined number of bi-phase encoded bits are detected (the runin length can be set in the x_cdrri register), the i-part and the pll oscillator will be set and the pll will be locked. when x_cdrri.runlen is set to small values, then the i-part is less accurate (residual error) and can lead to a longer needed pll settling time and worse performance in the timing extrapolation symbol sync found eom x_cdrri x_tsimode (tsigrsyn) recover ed clock phase detector pi loop filter digital controlled oscillator x_tvwin x_ t si ga p (gapval) x_cdrp x_cdri t nom / 16 t nom / 2 t nom / 2 from clock recovery slicer x_cdrtolb x_cdrtolc cdrdrthrn cdrdrthrp TDA5235 functional description data sheet 44 v1.0, 2010-02-19 first following bits. therefore the selected default value is a good compromise between fast symbol synchronization and accuracy/performance. duty cycle and data rate acceptance limits are adjustable via registers. after locking, the clock must be stable and must follow the reference input. therefore, a rapid settling procedure (timing extrapolation unit) and a slow pll are implemented. if the pll is locked, the reference signal from the clock recovery slicer is used in the phase detector block to compute the actual error. the error is used in the pi loop filter to set the digital controlled oscillator running frequency. for the p, i and timing extrapolation unit settings , the default values for the x_cdrp and x_cdri control registers are recommended. the pll will be unlocked, if a code violation of more than the defined length is detected, which is set in the x_tvwin control register. another criterion for pll resynchronization is an end of message (eom) signalled by the framer block. the pll oscillator generates the chip clock (2 * f data ). the internal pll lock signal used by the framer is generated up to 1 bit before runin ends. the timing extrapolation unit counts the incoming edges and interprets the delay between two edges as a bit or a chip. due to the fact that the first edge of a ?low? bit, coded as ?0? and ?1?, rises one chip later than a ?high? bit, the pll locks later in this case (see figure 20 ). the real needed runin time can be shorter than the configured runin length in the x_cdrri register by up to two chips. this should be considered when setting the tsi pattern and/or tsi length. see also chapter 2.4.8.6 frame synchronization . figure 20 runin generation principle 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 runin first edge 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 runin first edge 0 1 4 bits detected 4 bits detected data sheet 45 v1.0, 2010-02-19 TDA5235 functional description number of required runin bits the number of runin bits spec ified in x_cdrri register should always be 3.0. this setting defines the duration of the internal synchronization. because of internal processing delays, the pattern length that must be reserved for runin is longer. the ideal runin pattern is a se ries of eit her manchester 1?s or manchester 0?s. this pattern includes the highest number of edges that can be used for synchronization. in this case, the number of physically sent runin bits is 4. for any other runin pattern, 5.5 bits should be reserved for runin. tvwin (timing violation window length) the pll unlocks if the reference signal is lost for more than the time defined in the x_tvwin register. during the tsi gap (see tsi gap mode in chapter 2.4.8.6 frame synchronization ), the pll and the tvwin are frozen. tvwin time is the time during which the digital baseband receiver should stay locked without any incoming signal edges detected. the time resolution is t/16. calculation of tvwin can be seen at the end of subsection tsi gap mode in chapter 2.4.8.6 frame synchronization . TDA5235 functional description data sheet 46 v1.0, 2010-02-19 duty cycle variation ideally, the input signal to the clock and data recovery (cdr) would have a chip width of 8 samples and a bit width of 16 samples and the cdr would not lock onto any input that violates this. however, due to variations in the duty cycle this stringent assumption for the pulse widths will in general not be true. therefore it is necessary to loosen this requirement by using tolerance windows. figure 21 definition of tolerance windows for the cdr there exist now two registers - x_cdrtolc for the chip width tolerance and x_cdrtolb for the bit width tolerance - that can be used to tighten or loosen the windows around the ideal pulse widths. as it can easily be seen from figure 21 , tighter windows will result in more stringent requirements for the input data to have a 50% duty cycle and bigger windows will allow the duty cycle to vary more. figure 21 also depicts the meaning of the bits in the registers x_cdrtolc and x_cdrtolb. lim_chip_low = 8 - tolchipl lim_chip_high = 8 + tolchiph lim_bit_low = 16 - tolbitl lim_bit_high = 16 + tolbith tolchipl tolchiph tolbitl tolbith 1 t data sheet 47 v1.0, 2010-02-19 TDA5235 functional description data rate acceptance limitation the clock and data recovery is able to accept data rate errors of more than +/-15% with a certain loss of performance. there exist multi-configuration applications where the data rate of both configurations are within this range. so the adjacent data rates of these configurations are disturbing each other. the limitation of the data rate acceptance can be activated in this case. figure 22 data rate acceptance limitation the clock and data recovery (cdr) regenerates the clock based on the input data delivered from the clock recovery (cr) slicer. symbol synchronization (cdr_lock) is achieved when a specified number of chips (can be se t via register x_cdrri.runlen) has a valid pulse width. in parallel the preset value correlator estimates a preset value for the clock recovery pll so that a shorter settling time is achieved. this preset value is also proportional to the data rate and is therefore used in the data rate acceptance limitation block. if the preset value is outside a certain range (positive and negative threshold configur able via regi sters cdrdrthrp and cdrdrthrn), the cdr does not go into lock and no symbol synchronization is generated. for each configuration there exists one bi t (register x_cdrri.drlim en) to switch the data rate acceptance limitation functionality on or off. data rate acceptance limitation is disabled by default. all configurations share the same threshold registers, the default clock recovery slicer symbol synchronization preset value correlator clock recovery pll data rate acceptance limitation & clock recovery cdr_clock cdr_lock TDA5235 functional description data sheet 48 v1.0, 2010-02-19 thresholds are set so that almost all packets with a data rate error of +/-10% and larger are rejected. the following statements summarize some important aspects that need to be kept in mind when using the described functionality: ? the output of the estimator must be described on statistical terms - this means that it can not be guaranteed that all packets with a certain data rate outside the allowed range will be rejected ? the quality of the estimated data rate value is mainly influenced by the setting of the signal and noise detectors ? reducing the runin length in register x_cdrri reduces the quality of the data rate estimation, resulting in a degradation of the performance of the data rate acceptance limitation block ? the same threshold can be used for fsk and ask ? if the thresholds are too small it may happen that also packets with a valid data rate are rejected 2.4.8.4 data slicer and line decoding the output signal of the matched filter within the internal data processing path is in the range of +x to -x (x is the maximum value of the internal bit width). if code violations within a manchester encoded bitstream have to be detected, the data slicer has to recover the underlying chipstream instead of the bitstream. in this case zero values at the matched filter output lead to an additional slicing threshold and an implicit sensitivity loss. to provide the full reachable sensitivity for applications which do not need the symbols s (space) and m (mark), the data slicer has two different operating modes: ? chip mode (code violations are allowed) ? bit mode (without code violations) the chip mode introduces an implicit sensitivity loss compared to the bit mode, because a zero-crossing in the 2-chip matched filter signal must be detectable. this is only possible when an additional slicing level is introduced in the data slicer. the data slicer internally maps a positive value to a 1 and a negative value to a -1. everything inside the zero thresholds (zero-tube) becomes a 0. after that, the decoding to the chip-level representation is done by mapping the -1 to a "0" chip and the 1 to a "1" chip. a zero out of the data slicer is decoded to chip-level by referencing to the previous chip value. data sheet 49 v1.0, 2010-02-19 TDA5235 functional description in bit mode the data slicer has only one threshold (zero) to distinguish between the two levels of the matched filter output. the data slicer internally maps a positive value to a 1 and a negative value to a -1. after that, the selected line decoding is applied. summary of data slicer modes in the TDA5235: data slicer chip mode: ? code violations detectable (tsi, or eom) ? performance loss compared to bit mode ? activation via setting register x_slccfg to a value of + 0x90 (chip mode eom-cv: for patterns with code violations in data packet and optimized for activated eom code violation criterion (and optional eom data length criterion)) + 0x94 (chip mode eom-data length: for patterns with code violations in data packet and optimized for activated eom data length criterion only) + 0x95 (chip mode transparent: when framer is not used, but ch_data / ch_str are used for data processing) data slicer bit mode: ? no code violations detectable ? full performance ? in case of bi-phase mark and bi-phase space an additional bit must be sent to ensure correct decoding of the last bit ? activation via setting register x_slccfg to a value of 0x75 in data slicer bit mode an even number of tsi chips needs to be used. when data slicer bit mode is selected, then the the last chip of runin must be different from first chip of tsi (e.g. runin-bit sequence 000000 and tsi bit sequence 0xx...xxx is ok). otherwise the tsi will not be detected correctly. on using data slicer bit mode, the wake-up criteria equal bits detection and pattern detection cannot be applied. a line decoder decodes the incoming data chips according to the encoding scheme (see chapter 2.4.8.2 ). TDA5235 functional description data sheet 50 v1.0, 2010-02-19 2.4.8.5 wake-up generator a wake-up generation unit is used only in the self polling mode for the detection of a predefined wake-up criterion in the received pattern. there are two groups of configurable wake-up criteria: ? wake-up on level criteria ? wake-up on data criteria the search for the wake-up data criterion is started if data chip synchronization has occurred within the predefined number of symbols, otherwise the wake-up search is aborted. several different wake-up patterns, like random bit, equal bit, bit pattern or bit synchronization, are programmable. additional level criterion fulfilment for rssi or signal recognition can lead to a fast wake-up and to a change to run mode self polling. whenever one of these wake-up level criteria is enabled and exceeds a programmable threshold, a wake-up has been detected. the wake-up level criterion can be used very effectively in combination with the ultrafast fall back to sleep mode (see chapter 2.6.2.3 ) for further decreasing the needed active time of the autonomous receive mode. a configurable observation time for wake-up on level can be set in the x_wulot register. the wake-up on level criterion can be handled very quickly for fsk modulation, while in case of ask the nature of this modulation type has to be kept in mind. data sheet 51 v1.0, 2010-02-19 TDA5235 functional description figure 23 wake-up generation unit wake-up on rssi the threshold x_wurssith1 is used to decide whether the actual signal is a wanted signal or just noise. any kind of interfering rssi level can be blocked by using an rssi blocking window. this window is determined by the thresholds x_wurssibl1 and 16-chips shift register pattern detector bit change detector wake-up window chip counter x_wubcnt x_wupat0 x_wupat1 chip data chip data clock sync wu wake-up generation fsm no wu sync search time elapsed code violation detector 015 2 wuw chip counter elapsed code violation detected bit change detected pattern detected 3 16 x_wuc selection pattern equal bits random bits sync signal recognition rssi wu level criterion compare rssi level x_wurssith1 exceeding threshold wake-up on signal recognition data x_ndthres exceeding threshold (s) x_ndconfig x_sigdet1 x_sigdetlo wu on level criteria wu on data criteria x_wurssibl1 x_wurssibh1 TDA5235 functional description data sheet 52 v1.0, 2010-02-19 x_wurssibh1. these two thresholds can be evaluated during normal operation of the application to handle the actual interferer environment. the blocking window can be disabled by setting x_wurssibh1 to the minimum value and x_wurssibl1 to the maximum value. figure 24 rssi blocking thresholds threshold evaluation procedure a statistical noise floor evaluation using read register rssipmf (rms operation) leads to the threshold x_wurssith1. the interferer thresholds x_wurssibl1 and x_wurssibh1 are disabled when they are set to their default values. for evaluation of the interferer thresholds, either use register rssipmf for rms operation or during spm and wu (wake-up) on rssi use register rssipwu to statistically evaluate the interferer band. finally the thresholds x_wurssibl1 and x_wurssibh1 can be set. wake-up on rssi can also be applied as additional criterion when already using a wake-up on data criterion in constant on-off (coo) mode. further details can be seen in figure 10 , chapter 2.4.7 rssi peak detector , chapter 2.6.2.2 constant on-off time (coo) and chapter 2.6.2.3 fast fall back to sleep (ffb) . note: if e.g. an interferer ends/starts too close after/to the beginning/end of the observation time, then a decision level error can arise. this is due to the filter dynamics (settling time). further, for interferer thresholds evaluation in spm this changes interferer statistics. several interferer measurements are recommended to suppress this, what makes sense anyway for a better distribution. noise floor wanted signal interferer wanted signal x_wurssith1 x_wurssibl1 x_wurssibh1 rssi magnitude data sheet 53 v1.0, 2010-02-19 TDA5235 functional description wake-up on signal recognition instead of the previously mentioned rssi criterion, the signal recognition criterion (see chapter 2.4.8.1 ) can be applied for wake-up search. so the x_sigdet1, x_sigdetlo and x_ndthres threshold registers can be used. the observation time has to be specified in the register x_wulot. this observation time has to contain the delay in the signal path (12.5 s + 2.25*t bit ) and the duration for the comparison of the signal recognition criterion. the number of consecutive valid signal recognition samples/levels is compared vs. a threshold defined in x_wurssibh1 register. please note that x_wurssibh1 register is used for both wake-up on rssi and wake-up on signal recognition function. this threshold has an influence on the false alarm rate. so x_wurssibh1 defines the minimum needed consecutive t/16 samples of the signal recognition output to be at high level for a positive wake-up event generation. wake-up on data criterion all sfrs configuring the wake-up generation unit support the multi-configuration capability. the search for a wake-up data criterion is started if symbol synchronization is given within a certain duration (see chapter 2.4.8.8 runin, synchronization search time and inter-frame time ); otherwise the wake-up search is aborted. during the observation period, the wake-up data search is aborted immediately if symbol synchronization is lost. if this is not the case, the wake-up search will last for the number of chips/bits defined in the register x_wubcnt. the wake-up window (wuw) chip/bit counter counts the number of received chips/bits and compares this number vs. the number of chips/bits defined in the register x_wubcnt. the code violation detector checks the incoming chip data stream for being bi-phase coded. a code violation is given if three consecutive chips are ?one? or ?zero?. the bit change detector checks the incoming bi-phase coded bit data stream for changes from 'zero' to 'one' or 'one' to 'zero'. the pattern detector searches for a pattern with 16 chips/bits length within the wake-up window. the pattern is configurable via the registers x_wupat0 and x_wupat1. on using data slicer bit mode, the wake-up criteria equal bits detection and pattern detection cannot be applied. further details can be seen at the end of chapter 2.4.8.4 . the selection of 1 out of 4 wake-up data criteria is done via the x_wuc register. TDA5235 functional description data sheet 54 v1.0, 2010-02-19 details on the four wake-up data criteria pattern detection the incoming signal must match a dedicated pattern of up to 8 bits or 16 chips in wake- up pattern chip mode. when the wuw chip counter elapses, the search is stopped. the higher the setting of wubcnt the longer it is possible to search for the wake-up pattern. the minimum for the wubcnt is 0x11! the pattern detection is stopped either when wuw elapses, or when symbol synchronization is lost. the wake-up pattern can be extended from 16 chips to 16 bits on activation of wupmsel bit (wake-up pattern bit mode). in this bit mode no code violations (cv) are allowed and thus pattern detection is aborted, when a cv is detected. equal bits detection wake-up condition is fulfilled if all received bits inside of wuw are either 0 or 1. wubcnt holds the number of required equal bits. the higher the setting of wubcnt the lower the number of wrong wake-ups. equal bits detection is stopped if a bit change or a cv has been detected, or symbol synchronization is lost. random bits detection wake-up condition is fulfilled if there is no code violation inside of wuw. wubcnt holds the number of required bi-phase coded bits. the higher the setting of wubcnt, the lower the number of wrong wake-ups. random bits detection is stopped if a code violation has been detected, or symbol synchronization is lost. valid data rate detection wake-up condition is fulfilled if symbol synchronization is possible inside of sync search time out (see chapter 2.4.8.8 runin, synchroniz ation search time and inter- frame time ). wubcnt is not used. this is the weakest wake-up data criterion, and should be avoided. data sheet 55 v1.0, 2010-02-19 TDA5235 functional description figure 25 wake-up data criteria search 2.4.8.6 frame synchronization the frame synchronization unit (framer) synchronizes to a specific pattern to identify the exact start of a payload data frame within the data stream. this pattern is called telegram start identifier (tsi). there are different tsi modes selectable via the configuration: ? 16-bit tsi mode, supporting a tsi length of up to 16 bits or 32 chips ? 8-bit parallel tsi mode, supporting two independent tsi pattern of up to 8 bits length each. different payload length is possible for these two tsi pattern. ? 8-bit extended tsi mode, identical to 8-bit parallel tsi mode, but identifies which pattern matches by adding a single bit at the beginning of the data frame ? 8-bit tsi gap mode, supporting two independent tsi pattern separated by a discontinuity all sfrs configuring the frame synchronization unit support the multi-configuration capability (config a and b). the framer starts working in run mode slave after symbol sync found and in self polling mode after wake-up found and searches for a frame until tsi is found or synchronization is lost. the input of the framer is a sequence of bi-phase reset wu=0 no wu=0 idle pattern detection random bits detection equal bits detection ssync=1 wakeup criteria=random bits detection no wake-up wu=1 no wu=0 wake-up ssync search time elapsed = 1 wu=0 no wu=1 wu=0 no wu=0 ssync=1 wakeup criteria=pattern detection ssync =0 ssync =0 wu=0 no wu=0 wu=0 no wu=0 init wakeup unit pattern match=1 wuw chip counter < wubcnt ssync=0 cv=1 wuw chip counter < wubcnt wuw chip counter data sheet 57 v1.0, 2010-02-19 TDA5235 functional description please note that for data slicer bit mode a special constellation of runin bits and tsi bits has to be ensured. further details can be seen at the end of chapter 2.4.8.4 . the two independent correlators can be configured in the x_tsimode register to work in one of the following four tsi modes: 16-bit mode: as a single correlator of up to 32 chips the length of the x_tsilena register must be set to 16d whenever x_tsilenb is higher than 0. figure 27 16-bit tsi mode 8-bit parallel mode: as two correlators of up to 16 chips length each working simultaneously in parallel in the following example, tsi pattern b matches first and generates an fsync. the lengths of both tsi patterns are now independent from each other. the payload length for these two tsi pattern may be different. figure 28 8-bit parallel tsi mode incoming pattern 0 0 0 0 manchester coded 0 1 0 1 0 0 0 1 1 1 1 1 0 1 0 0 1 0 tsi pattern match 01010101011001100101011010101010011001011001 runin 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 1 0 1 1 0 0 fsync data into fifo 1 0 1 0 0 1 0 x_tsilena = 16d, x_tsilenb = 6d 543210 6 7 13121110 9 8 14 15 x_tsipta 543210 x_tsiptb incoming pattern manchester coded tsi pattern b match 0101010101100110011001011001 runin 0 0 0 1 1 1 fsync data into fifo 543210 x_tsiptb x_tsilena = 16d, x_tsilenb = 6d 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 TDA5235 functional description data sheet 58 v1.0, 2010-02-19 8-bit extended mode: as two correlators of up to 16 chips length each working simultaneously in parallel, with matching information insertion this bit is inserted at the beginning of the payload. ?0? is inserted, when correlator a has matched and ?1? when correlator b has matched. the payload length for these two tsi pattern may be different. figure 29 8-bit extended tsi mode 8-bit gap mode: as two sequentially working correlators of up to 16 chips length each this mode is only used in combination with the tsi gap mode shown below! this mode is used to define a gap between the two patterns which is preset in the x_tsigap register. to identify exactly the beginning of the gap it would be helpful on occasion to place the first cv of the gap into the tsi pattern a. in this case, the gap length needed for the x_tsigap register must be shortened and the x_tvwin length must be extended. figure 30 8-bit gap tsi mode incoming pattern 0 0 0 0 manchester coded 0 1 0 1 0 1 0 0 1 0 tsi pattern b match 0101010101100110011001011001 runin fsync data into fifo 1 0 1 0 0 1 0 x_tsilena = 16d, x_tsilenb = 6d 1 matching information inserted 0 0 0 1 1 1 543210 x_tsiptb incoming pattern 0 0 0 0 manchester coded 0 1 0 1 0 0 0 1 1 1 1 1 0 1 tsi pattern match 01010101011001000000010101011001010110101010100110 runin 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 1 0 fsync data into fifo 1 0 1 x_tsilena = 8d, x_tsilenb = 12d tsigrsyn = 1 0 0 0 0 runin gap 1 1 s 0 0 543210 6 7 1110 9 8 x_tsiptb 543210 x_tsipta 6 7 data sheet 59 v1.0, 2010-02-19 TDA5235 functional description selection of a tsi pattern tsi patterns must be different to the wake-up bit stream and the runin to clearly mark the start of the following payload data frame. it should be considered that the synchronization has a tolerance of about one bit. in addition, synchronization is related to data chips, and may occur in the middle of a data bit. this all must be tolerated by the data framer. further details can be seen in chapter 2.4.8.3 clock and data recovery . ideal tsi patterns have a unique bit combination at their end, which may also contain a number of code violations (cvs), when possible (see chapter 2.4.8.4 data slicer and line decoding ). some examples of tsi patterns: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 when cvs are used: 0 0 0 0 0 0 0 0 0 0 0 0 0 m 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 m 0 note: cvs in a tsi are practical for better differentiation to the real data, especially if repetition of data frames is used for wake-up. end of message (eom) detection an end of message (eom) detection feature is provided by the eom detector. three criteria can be selected to indicate eom. the first is based on the number of received bits since frame synchronization. the number of expected bits is preset in the x_eomdlen register. sending fewer bits as defined in the register will result in no eom. the eom counter will be reset after new frame synchronization. in 8-bit parallel tsi mode and 8-bit extended tsi mode, the payload length for the two independent tsi pattern may be different. therefore the payload length for tsi b pattern can be preset in the x_eomdlenp register, while payload length for tsi a pattern can be preset in the x_eomdlen register. the second criterion is the detection of a code violation. this eom criterion is not applicable for data slicer bit mode. TDA5235 functional description data sheet 60 v1.0, 2010-02-19 the third criterion is the loss of symbol synchronization. depending on the x_tvwin register, the sync signal persists for a certain amount of time after the end of the pattern has been reached. therefore, more bits could be written into the fifo than sent. the three eom criteria can be combined with each other. if one of the selected eom criteria is fulfilled, an eom signal will be generated. tsi gap mode the tsi gap mode is only used if tsi patterns contain a gap that is not synchronous to the data rate, e.g. if a gap is 7.7 data bits, or if a gap is longer than 10 data bits. in all other cases, gaps should be included in the tsi pattern as code violations. because of its complexity in configuration, tsi gap mode should be only used in applications as noted above! for these special protocols, it is possible to lock the actual data frequency during a long code violation period inside a tsi (x_tsigap must have a minimum of 8 chips). tsigap is used to lock the pll after tsi a was found. after the lock period, two different resynchronization modes are available (tsi gap resynchronization, tsigrsyn): ? frequency readjustment (pll starts from the beginning), tsigrsyn = 1. in this mode the t/2 gap resolution can be set in the 5 msb x_tsigap register bits. the value in gapval (3 lsb in x_tsigap register) is not used. this is the preferred mode in tsi gap mode. figure 31 clock recovery gap resynchronization mode tsigrsyn = 1 ? phase readjustment only, tsigrsyn = 0. in this mode, the value in gapval is used to correct the phase after the gap phase. overall gap time can be defined in t/16 tsi a tsi gap tsi b valid data valid data a l l s p a c e o r a l l m a r k clock recovery reset start point pll sync internal pll sync runin gapsync < 1bit < 1bit data sheet 61 v1.0, 2010-02-19 TDA5235 functional description steps. the 5 msb bits (tsigap) define the real gap time and the 3 lsb bits (gapval) the dco (digital controlled oscillator) phase correction value. figure 32 clock recovery gap resynchronization mode tsigrsyn = 0 when the time tsi gap in the start sequence of the transmitted telegram has elapsed, the receiver needs a certain time (gapsync = 5...6 chips) to readjust the pll settings. behavior of the system at the starting position of the tsi b: the starting position (tsi b start) for the tsi b comparison is independent from the runin settings (x_cdrri register) and the resynchronization mode (x_tsimode register): the incoming chips at tsi b start and the following incoming chips are compared with the contents of the register tsi b. please notice that the receiver?s pll runs at the data rate determined before the gap. therefore, the receiver calculates the gap based on this data rate. behavior of the system at the ending position of tsi b: the system checks for the tsi b to match within a limited time. if there is no match within this time, then the receiver starts again to search for the tsi a pattern at the following incoming chips: for a successful tsi b pattern match, the defined tsi b pattern must be between ?start of tsi b? and ?stop of tsi b?. in the example below, the earliest possible start position would be the 18 th chip and the latest possible start position would be the 22 nd chip. tsi a tsi gap gapsync tsi b valid data valid data all space or all mark clock recovery phase readjustment start point pll sync runin < 1bit tsibstart chips [] tsigap chips [] 6 8 + = tsibstop chips [] tsigap chips [] tsilenb chips [] 11 ++ = TDA5235 functional description data sheet 62 v1.0, 2010-02-19 please note that after a gap, the internal tsi comparison register is cleared (all chips set to ?0?). in this case, a tsi b criteria of ?0000? would always match at the beginning. to avoid such an unwanted matching, set the highest tsi b match chip to ?1?. figure 33 tsigap tsib timing the tvwin (timing violation window) and tsigap dependency is shown in figure 34 . figure 34 tvwin and tsigap dependency example tvwin calculation for pattern without gap time: the entire tvwin time is made up of the cv 1) number itself, the half bit before cv and the half bit after the cv. to reach all frequency and duty cycle errors, 25% of the overall sum must be added. tvwin calculation with gap time: 1) cv...number of bits containing manchester code violations incoming pattern[bits] ... 0 0 1 0 1 0 0 0 1 1 1 1 1 runin 0 0 0 0 gapsync tsigap=10 chips s tsia _ _ _ _ _ tsibstart 1 start of tsib comparison 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 tsib 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 stop of tsib comparison cv tvwin tvwin gap tvwin tsia tvwin without gap tvwin with gap int. delay runin/ tsigrsyn = 1 tvwin round 8 16 cv ? 8 ++ () 1.25 ? () = tvwin round max 8 16 cv ? 8 ++ () 1.25 ? () 816tsia ? cv 16 1 ? 8 +++ () 1.25 ? , {} () = data sheet 63 v1.0, 2010-02-19 TDA5235 functional description 2.4.8.7 message id scanning this unit is used to define an id or special combination of bits in the payload data stream, which identifies the pattern. all sfrs configuring the message id scanning unit feature the multi-configuration capability. furthermore, it is available in the slave and self polling mode. the mid unit can be mainly configured in two modes: 4-byte and 2-byte organized message id. for each configuration there are 20 8-bit registers designed for id storage. sfrs are used to configure the mid unit: enabling of the mid scanning, setting of the id storage organization, the starting position of the comparison and number of bytes to scan. when the message id scanning unit is activated, the incoming data stream is compared bit-wise serially with all stored ids. if the scan end position is reached and all received data have matched the observed part of at least one mid the message id scanning unit indicates a successful mid scanning to the master fsm, which generates an mid interrupt. please note that the default register value of the mid registers is set to 0x00. all mid registers must be set to a pattern value to avoid matching to default value 0x00. if the mid unit finishes id matching without success, the data receiving is stopped and the fsm waits again for a frame start criterion. the received bits are still stored in the fifo. TDA5235 functional description data sheet 64 v1.0, 2010-02-19 4-byte organized message id: in this mode four bytes are merged to define an id-pattern. this does not mean that the id must be exact four bytes long. the number of bytes used is defined in register x_midc1. up to 5 id patterns are available. figure 35 4-byte message id scanning line selector combiner line number x_mid0 8 x_mid1 8 x_mid2 8 x_mid3 8 x_mid4 8 x_mid5 8 x_mid6 8 x_mid7 8 x_mid8 8 x_mid9 8 x_mid10 8 x_mid11 8 x_mid12 8 x_mid13 8 x_mid14 8 x_mid15 8 x_mid16 8 x_mid17 8 x_mid18 8 x_mid19 8 32 mid0:mid3 32 mid4:mid7 32 mid8:mid11 32 mid12:mid15 32 mid16:mid19 control- fsm da ta c lock x_midc0 x_midc1 mid scanning finished bit counter s c a n n e r bit0 bit31 scan start position reached scan end position reached mid found enable mid scanning init mid scanner interface to master fsm da ta from digital-receiver mid match number to scan organization number of startbit enable scanner data sheet 65 v1.0, 2010-02-19 TDA5235 functional description 2-byte organized message id: in this mode two bytes are merged to define an id pattern. up to 10 patterns are possible. figure 36 2-byte message id scanning id position configuration: it is possible to choose which part of the incoming data stream is compared against the stored mids. the register x_midc0 contains the scan start position. if the bit counter detects the scan start position, the control fsm enables the scanner. the register x_midc1 contains the number of bytes to scan. during the observation period, the line selector combiner line number x_mid0 8 x_mid1 8 x_mid2 8 x_mid3 8 x_mid4 8 x_mid5 8 x_mid6 8 x_mid7 8 x_mid8 8 x_mid9 8 x_mid10 8 x_mid11 8 x_mid12 8 x_mid13 8 x_mid14 8 x_mid15 8 x_mid16 8 x_mid17 8 x_mid18 8 x_mid19 8 control- fsm da ta clock x_midc0 x_midc1 mid scanning finished bit counter s c a n n e r bit0 bit15 scan start position reached scan end position reached mid found enable mid scanning init mid scanner interface to master fsm da ta from digital-receiver mid match number to scan organization number of startbit enable scanner 16 mid0:mid1 16 mid2:mid3 16 mid4:mid5 16 mid6:mid7 16 mid8:mid9 16 mid10:mid11 16 mid12:mid13 16 mid14:mid15 16 mid16:mid17 16 mid18:mid19 TDA5235 functional description data sheet 66 v1.0, 2010-02-19 message id scanning is aborted immediately by the master fsm, if symbol synchronization is lost or an eom (end of message) is detected. example: start selection: 00010001b number to scan: 00b, 01b, 10b, 11b figure 37 mid scanning the starting position in this case is bit 17. depending on the number to scan, the corresponding number of bytes is compared with the stored mids. 2.4.8.8 runin, sy nchronization search time and inter-frame time the functionality of the digital baseband receiver is divided into four consecutive data processing stages; the data filter, clock and data recovery, data slicer and frame synchronization unit. the architecture of the digital baseband receiver is optimized for processing bi-phase coded data streams. the basic structure of a payload frame is shown in figure 38 . the protocol starts with a so called runin. the runin wi th the minimum leng th of four bi-phase coded symbols is used for internal filter settling and frequency adjustment. the tsi (telegram start identifier), which is used as framing wo rd, follows the runin se quence. the payload contains the effective data. the length of the valid payload data is defined as the length itself or additional criteria (e.g. loss of sync). please note that almost all transmitted protocols send a wake-up sequence before the payload frame (see also figure 72 ). this wake-up sequence allows a very fast decision, whether there is a suitable message available or not. further details on this topic can be gained from chapter 2.6.1.5 and chapter 2.4.8.5 . 012 byte0 fsync byte2 byte3 start mid scan number to scan =00b number to scan =01b number to scan =10b number to scan =11b bit 17 18 23 24 25 26 31 32 33 34 39 40 41 42 47 48 49 byte0 byte0 byte0 byte1 byte1 byte2 first data bit byte1 data sheet 67 v1.0, 2010-02-19 TDA5235 functional description figure 38 structure of payload frame two important system parameters are described in this section: the sy nchronization s ea rc h t ime o ut (sysrcto) and the inter-frame time. the processing sequence of a payload frame is shown in figure 39 . figure 39 data latency the overall system latency time is calculated in two steps: t 1 is the delay between adc input (ask) / limiter output (fsk) and the cdr input, and t 2 is the time between symbol sync found and the framer output (decoded data available). t 4 is the time between symbol sync found and chip data output (rx mode tmcds). t 4 = 1 t. t is the nominal duration of one data bit. t 1 latency time include: (t 1 = 12.5s + 2 t) ? digital frontend processing delay ? matched filter computation time ? signal detector delay t 2 latency time include: (t 2 = 1.5 t + 0.5 t 1) ) ? data slicer computation time ? framer computation time. 1) the 0.5 t have to be added in case of activation of bi-phase mark / space decoding mode and data slicer bit mode without code violation (see register x_slccfg) runin tsi payload runin tsi input data tsi t 1 t 2 data available tsi cdr input runin runin runin eom eom eom t 2 t 2 pll r e -synchr onization t 3 sym bol sync found runin chip data available t 4 TDA5235 functional description data sheet 68 v1.0, 2010-02-19 the synchronization search time t 3 is the time the receiver requires to search for a pattern in an incoming data stream and needs to be considered in the receivers start-up phase. the minimum value of the search time out length is the consequence of the system latency time t 1 , the runin length and the time of asynchronism between transmitter and receiver. this means, that for the minimum length of register value for sysrcto, the value 2 bits plus 12.5 s plus the runin length, which is set in the x_cdrri register, plus 2 bits (to consider worst case runin patterns and tx-rx asynchronism) have to be used. to reach data rate and duty cycle errors, 10% of the overall sum must be added. a second important system parameter that must be considered, is the minimal inter- frame time (time between two data frames). this time is equal to the time t 2 and has a length of 1.5 or 2 bits 1) . the eom to pll resynchronization time is negligible in case initdrxes is disabled. otherwise t 1 has to be added. 2) note that the described inter-frame time is based on the input pattern with equal signal power in the following data frame; in other cases, the inter-frame time can vary from the calculated value. 1) see previous footnote 2) in case initdrxes is enabled sysrct0 roundup 12.5 s t bit ---------------- - 2runlen 2 ++ + ?? ?? 16 ? ?? ?? 1.1 ? ?? ?? = t inter frame ? 1.5t bit 0.5t bit 1 ) 0 ?? ?? ?? t 1 2 ) 0 ?? ?? ?? ++ = data sheet 69 v1.0, 2010-02-19 TDA5235 functional description 2.4.9 power supply circuitry the chip may be operated within a 5 volts or a 3.3 volts environment. figure 40 power supply for operation within a 5 volts environment (supply voltage range 1), the chip is supplied via the vdd5v pin. in this configuration the digital i/o pads are supplied via vdd5v and a 5 v to 3.3 v voltage regulator supplies the analog/rf section (only active in run modes). when operating within a 3.3 volts environment (supply voltage range 2), the vdd5v, vdda and vddd pins must be supplied. the 5 v to 3.3 v voltage regulators are inactive in this configuration. the internal digital core is supplied by an additional 3.3 v to 1.5 v regulator. the regulators for the digital section are controlled by the signal at p_on (power on) pin. a low signal at p_on disables all regulators and set the ic in power down mode. a low to high transition at p_on enables the regulators for the digital section and initiates a power on reset. the regulator for the analog section is controlled by the master control unit and is active only when the rf section is active. to provide data integrity within the digital units, a brownout detector monitors the digital supply. in case a voltage drop of vddd below approximately 2.45 v is detected a reset will be initiated. vdd5v power-up brownout detector reset- circuit rf section analog section vddd vdda gnda gndrf digital-i/o vddd1v5 digital-core gndd p_on internal reset voltage regulator 3.3 1.5 v enable out in voltage regulator 5 3.3 v out in en able voltage regulator 5 3.3 v en able out in enable rx_run TDA5235 functional description data sheet 70 v1.0, 2010-02-19 a typical power supply application for a 3.3 volts and a 5 volts environment is shown in the figure below. figure 41 3.3 volts and 5 volts applications 5v vdda gnda gndrf vddd vdd5v vddd1v5 gndd supply -application in 3.3v environment TDA5235 3.3v 4.7 10 100n 100n 100n vdda gnda gndrf vddd vdd5v vddd1v5 gndd TDA5235 100n 100n 100n *) 1 *) 22 *) when operating in a 5v environment, the voltage-drop across the voltage regulators 5 ? 3.3v has to be limited , to keep the regulators in a safe operating range. resistive or capacitive loads (in excess to the scheme shown above) on pins vdda and vddd are not recommended. supply-application in 5v environment 4.7 100n 100n data sheet 71 v1.0, 2010-02-19 TDA5235 functional description 2.4.9.1 supply current in sleep mode, the master control unit switches the crystal oscillator into low power mode (all internal load capacitors are disconnected) to minimize power consumption. this is also valid for self polling mode during off time (spm_off). whenever the chip leaves the sleep mode/spm_off (t 1 ), the crystal oscillator resumes operation in high precision mode and requires t coscsettle to settle at the trimmed frequency. at t 2 the analog signal path (rf and if section) and the rf pll are activated. at t 3 the chip is ready to receive data. the chip requires t rxstartup when leaving sleep mode/spm_off until the receiver is ready to receive data. a transient supply current peak may occur at t 1 , depending on the selected trimming capacitance. the average supply current drawn during t rfstartdelay is i rf-fe-startup,bpfcal . figure 42 supply current ramp up/down if the if buffer amplifier or the clock generation feature (ppx pin active) are enabled, the respective currents must be added. i sleep_low i rf-fe-startup ,bpfcal i run t c osc settle t supply current run mode*) sleep mode**) spm off time t on rx_run signal t 3 t 2 t 1 *) run mode covers the global chip states : run mode slave / receiver active in self polling mode / run mode self polling **) i sleep_low is valid in the chip states : sleep / off time during self polling mode t rxstartup t rfstartdelay (t off )(t off ) TDA5235 functional description data sheet 72 v1.0, 2010-02-19 2.4.9.2 chip reset power down and power on are controlled by the p_on pin. a low at this pin keeps the ic in power down mode. all voltage regulators and the internal biasing are switched off. a high transition at p_on pin activates the appropriate voltage regulators and the internal biasing of the chip. a power up reset is generated at the same time. figure 43 reset behavior a second source that can trigger a reset is a brownout event. whenever the integrated brownout detector measures a voltage drop below the brownout threshold on the digital internal reset supply voltage falls below reset- / brownout-threshold reset- / brownout- threshold (typ. 2.45v) 3v supply voltage at vddd pin t reset t functional- threshold (typ. 2v) reset- / brownout- threshold (typ. 2.45v) 3v voltage at pp2 pin (nint signal) functional- threshold (typ. 2v) a ?low? is generated at nint signal supply voltage falls below functional -threshold level on nint signal is undefined supply voltage rises above functional -threshold a ?low? is generated at pp2 pin (nint signal) c reads interrupt- status-registe r a ?low? is generated at pp2 pin (nint signal) a ?high? is generated at pp2 pin (nint signal) t data sheet 73 v1.0, 2010-02-19 TDA5235 functional description supply, the integrity of the stored data and configuration can no longer be guaranteed; thus a reset is generated. while the supply voltage stays between the brownout and the functional threshold of the chip, the nint signal is forced to low. when the supply voltage drops below the functional threshold, the levels of all digital output pins are undefined. when the supply voltage raises above the brownout threshold, the ic generates a high pulse at nint and remains in the reset state for the duration of the reset time. when the ic leaves the reset state, the interrupt status register is0 is set to 0xff and the nint signal is forced to low. now, the ic starts operation in the sleep mode, ready to receive commands via the spi interface. the nint signal will go high, when the interrupt status register is read for the first time. TDA5235 functional description data sheet 74 v1.0, 2010-02-19 2.5 system interface in most applications, the TDA5235 receiver ic is attached to an external microcontroller. this so-called application controller executes a firmware which governs the TDA5235 by reading data from the receiver when data has been received on the rf channel and by configuring the receiver device. the TDA5235 features an easy to use system interface, which is described in this chapter. transparent mode the TDA5235 supports two levels of integration. in the most elementary fashion, it provides a rather rudimentary interface by which the incoming rf signal is demodulated and the corresponding data is made available to the application controller. optionally, a chip clock is generated by the TDA5235. since the data signal is always directly the baseband representation of the rf signal, we call this mode the transparent mode. the usage of the transparent mode will be described in chapter 2.5.1.2 . packet oriented mode alternatively, the TDA5235 features the so-called packet oriented mode which supports the autonomous reception of data telegrams. the packet oriented mode provides a high-level system interface which greatly simplifies the integration of the receiver in data-centric applications. in packet oriented mode, the data interface is based on chunks of synchronous data which are received in packets. in the easiest way, the application controller only reacts on the synchronous data it receives. the receiver autonomously handles the line decoding and the deframing of these data, and supports the timed reception of packets. data is buffered in a receive fifo and can be read out via the data interface. further, the receiver provides support for the identification of wake-up signals. details on the usage of the packet oriented mode of the receiver are given in chapter 2.5.1.2 . 2.5.1 interfacing to the TDA5235 the TDA5235 is interfacing with an application by three logical interfaces, see figure 44 . the rf/if interface handles the reception of rf signals and is responsible for the demodulation. its physical implementation has been described in chapter 2.4.3 and chapter 2.4.8 , respectively. the other two logical interfaces establish the connection to the application controller. note that due to the high level of integration of the receiver, these interfaces impose minor requirements on the application controller, which can be as simple as an 8-bit microcontroller operated at low clock rate. as will be shown later, the physical implementation of the data interface depends on whether the receiver is operated in packet oriented or in transparent mode. for the sake of clarity, the communication between the TDA5235 and the application controller is split into control flow and data flow . this separation leads to an independent definition of the data interface and the control interface, respectively. data sheet 75 v1.0, 2010-02-19 TDA5235 functional description figure 44 logical and electrical system interfaces of the TDA5235 2.5.1.1 control interface the control interface is used in order to configure the TDA5235 after start-up or to re- configure it during run-time, as well as to properly react on changes in the status of the receiver in the application controller?s firmware. the control interface offers a bi- directional communication link by which ? configuration data is sent from the application controller to the TDA5235, ? the receiver provides status information (e.g. the status of a data reception) as response to a request it has received from the application controller, and ? the TDA5235 autonomously alerts the application controller that a certain, configurable event has occurred (e.g. that a packet has been received successfully). configuration and status information are sent via the 4-wire spi interface as described in chapter 2.5.5 . the configuration data determines the behavior of the receiver, which comprises ? scheduling the inactive power-saving phases as well as the active receive phases, ? selecting the properties of the rf/if interface configuration (e.g. carrier frequency selection, filter settings), ? configuring the properties of the frames (e.g. wake-up patterns, telegram start identifier (tsi), and optionally specifying the position, format and content of patterns within packets that stimulate a certain, configurable alerting behavior (message id)). note that the TDA5235 receiver ic supports reception of up to two configuration sets on a single channel each in a time-based manner without reconfiguration. thus, the rf/if interface as well as the frame format properties support alternative settings, which can be activated autonomously by the receiver as part of the scheduling process. in contrast to the high-level interface used for communicating configuration instructions and status information, alerts are emitted by the receiver on a digital output pin that may trigger external interrupts in the application controller. note that the alerting conditions as well as the polarity of the output pin are configurable, see chapter 2.5.4 . TDA5235 application controller (c) rx data data interface configuration status & alerts control interface rf interface spi & dig. out spi / dig. out TDA5235 functional description data sheet 76 v1.0, 2010-02-19 2.5.1.2 data interface the data interface between the application controller and the TDA5235 receiver ic is used for the transport of the received data, see figure 44 . the physical implementation as well as the features of the data interface depend on the selected mode of operation. there are 5 possible receive modes: ? packet oriented fifo mode (pof) ? packet oriented transparent payload mode (potp) ? transparent mode - chip data and strobe (tmcds) ? transparent mode - matched filter (tmmf) ? transparent mode - raw data slicer (tmrds) access points for these receive modes can be seen in figure 15 . the possible combinations of receive modes and polling mode setup is noted in figure 45 . figure 45 receive modes packet oriented fifo mode (pof) in packet oriented fifo mode, data is transferred via the 4-wire spi bus. during receive operation, the incoming rf signal is demodulated in the rf/if interface, the line decoding is performed and the data, of which wake-up frames, data frame headers and optional footers have been stripped off, is stored in the rx fifo. then, the received data can be read from the rx fifo using the ?read fifo? command described in data sheet 77 v1.0, 2010-02-19 TDA5235 functional description chapter 2.5.2 and chapter 2.5.5 . the data which is read from the rx fifo is accompanied by information which contains the status of the respective receive operation. note that the availability of received data packets is communicated via alerts in the control interface. figure 46 data interface for the packet oriented fifo mode packet oriented transparent payload mode (potp) this mode is very similar to pof mode as data which is going into fifo is also available via rxd and rxstr signals (see chapter 2.5.3 digital output pins ). figure 47 data interface for the packet oriented transparent payload mode in the TDA5235, there are specific digital output lines (ppx pin) for the bi-phase decoded data and an appropriate strobe signal. during inactivity of the receiver, the line is in default mode switched to low. scheduler rx data data interface rx fifo framer line decoder rf interface bit synchronizer TDA5235 application controller scheduler rx data data interface rx fifo framer line decoder rf interface bit synchronizer TDA5235 application controller strobe TDA5235 functional description data sheet 78 v1.0, 2010-02-19 in default mode the strobe signal is active high and has a delay of t bit /16 relative to the data bit and a duration of t bit /2. the polarity of the strobe signal is programmable, this can be done via ppcfg2 register. figure 48 timing of the packet oriented transparent payload mode transparent mode - chip data and strobe (tmcds) the receiver?s simple plain data interface in this transparent mode is shown in figure 49 . in this mode, the demodulated data signal is made directly available on the data output pin of the data interface. concurrently, an estimate of the chip clock is optionally provided on the respective clock output line. note that a sensible chip clock can only be generated if the selected line encoding exhibits a constant chip rate. the chip clock generation can be significantly improved by using a run-in signal of alternating one-zero chips (maximum number of transitions within a data stream). figure 49 data interface for the transparent mode - chip data and strobe in the TDA5235, there is a specific digital output line for the chip clock estimate as well as for the data output line, which delivers the encoded chip data. during inactivity of the receiver, the line is in default mode switched to low. the ppx pin provides the estimated chip clock, if ch_str is selected. further details are given in chapter 2.5.3 . d n d n+1 t bit /16 t bit /2 rxd rxstr scheduler rx data data interface rf interface bit synchronizer TDA5235 application controller rx chip strobe data sheet 79 v1.0, 2010-02-19 TDA5235 functional description in default mode the ch_str signal is active high and has a delay of t chip /8 relative to the data chip and a duration of t chip /2. the polarity of the ch_str signal is programmable, this can be done via ppcfg2 register. figure 50 timing of the transparent mode - chip data and strobe transparent mode - matched filter (tmmf) the received data after the matched filter (two-chip matched filter) with an additional sign function is provided via the data_matchfil signal (ppx pin). in this mode sensitivity measurements with ideal data clock can be performed very simple. for further details see the block diagram in figure 15 . sensitivity in this transparent mode is significantly depending on the implemented clock and data recovery algorithm of the user software in the application controller. figure 51 data interface for the transparent modes tmmf / tmrds transparent mode - raw data slicer (tmrds) this mode supports processing of data even without bi-phase encoding (e.g. nrz coding) by providing the received data via the one-chip matched filter on the data signal (ppx pin). see more details in the block diagram in figure 15 . d n d n+1 t chip /8 t chip /2 ch_data ch_str scheduler rx data data interface rf interface TDA5235 application controller TDA5235 functional description data sheet 80 v1.0, 2010-02-19 sensitivity in this transparent mode is significantly depending on the implemented clock and data recovery algorithm of the user software in the application controller. the data interface can be seen from figure 51 . self polling capabilities are possible as well, but only constant on-off mode and wake- up on rssi makes sense. assume one of the TDA5235 configurations (e.g. configuration b) is set for external data processing mode. see also example in figure 52 . the needed on time (latency through TDA5235) is configured in the corresponding on time registers of the chip. the interrupt for wake-up config b (wub) is enabled and suitable rssi thresholds are set. if the rssi signal is in a valid threshold area, the TDA5235 changes to run mode self polling and an interrupt can be signaled to the application controller. in case the rssi signal is outside the valid threshold area, the chip stays in self polling mode and the external controller gets no interrupt (as the desired rssi level is not reached). it should be mentioned that all timeout timers (totims) should be disabled in the configuration set of the external processing mode as the microcontroller takes over the control (see sfr bit group extproc in the x_chcfg register). it is recommended to put this external configuration at the end of the on time within the polling cycle (so right before the off time). this is helpful when using the "exttotim" command (goto self polling mode, next configuration or configuration a; see figure 77 ). when the external configuration is the last configuration before the off time, then the next configuration within the polling cycle would be the sequence of the off time. when data is available and the rssi is within a valid threshold area, an interrupt is generated (nint). so the application controller can process the data and decide about valid data. in case the controller decides that wrong data was sent, the microcontroller can send the register command "exttotim" (see figure 77 and extpcmd register). when the microcontroller detects valid data, then the controller can send the register command "exteom found" (see figure 77 and extpcmd register) after completing the data reception. the functionality described above can also be used for other receive modes (mainly tmmf, tmcds), where the external microcontroller takes on responsibility for further data processing. data sheet 81 v1.0, 2010-02-19 TDA5235 functional description figure 52 external data processing the sfr bit group extproc in the x_chcfg register can be activated for each configuration set for an easier handling of external data processing by the application controller. depending on the intended transparent receive mode an activation of this function means: ? data path in front of framer unit is no longer closed (so that no data is going into framer unit accidentally) ? interrupts for fsync, mid and eom are deactivated internally ? some/all totim counters are deactivated ? some/all wake-up on data criteria are disabled ? wake-up on signal recognition is/is not disabled configb configa selfpolling mode selfpolling scenario sleep mode runmode selfpolling selfpolling / sleep interrupt signal for rssi runmode selfpolling selfpolling / sleep no input signal rssi level too low ? chip stays in self polling mode and sends no interrupt wrong input signal interrupt signal for rssi c detects invalid data and sends ?exttotim? ? goto spm off-time runmode selfpolling selfpolling / sleep good input signal interrupt signal for rssi c finished data reception, sends ?exteom found? TDA5235 functional description data sheet 82 v1.0, 2010-02-19 2.5.2 receive fifo the receive fifo is the storage of the received data frames and is only used in the pof mode. it is written during data reception. the host microcontroller is able to start reading via spi right after frame sync (interrupt) or in the most common case right after detection of eom (interrupt). the fifo can store up to 256 received data bits. if the expected data transmission contains more bits (note that in tsi 8-bit extended mode one bit is added in front of the real payload to indicate which of the two tsi pattern has matched), reading from fifo must start a certain time after frame sync to prevent an overrun. architecture the 256-bit receive fifo is based on a bit-addressable 2-port memory architecture. figure 53 receive fifo the write port is controlled by the digital receiver using the write address pointer. writing data into the fifo starts with the detection of a tsi. the write address pointer is incremented with each data clock signal generated by the digital receiver. the read port is controlled by the spi controller using the read address pointer. each bit read from the spi controller increments the read address pointer. the read and write address pointers jump from their maximum value (255 d ) to address zero. writing to the fifo stops at eom or after sync loss. write address pointer (up-counter) 1 of 16 decoder 1 of 16 decoder byte 0 reset byte 3 byte 2 byte 1 byte 4 byte 7 byte 6 byte 5 byte 8 byte 11 byte 10 byte 9 byte 12 byte 15 byte 14 byte 13 out 0 1 2 3 4 5 6 7 bit-address 0 1 2 3 4 5 6 7 in from digital- receiver data clock fsync data eom 1 of 16 decoder 16 to 1 mux read address pointer (up-counter) reset bit-address sclk write-port read-port enable sdo sdo-frame generator to spi-bus fifo- controller enable fifo-overflow # of valid bits fifolk 256-bit memory-array from digital- receiver initfifo initfifo fsinitfifo from fsm fifolk to fsm byte 16 byte 19 byte 18 byte 17 byte 20 byte 23 byte 22 byte 21 byte 24 byte 27 byte 26 byte 25 byte 28 byte 31 byte 30 byte 29 data sheet 83 v1.0, 2010-02-19 TDA5235 functional description fifo lock behavior the fifo possesses a lock mechanism that is enabled via the sfr control bit fifolk in the cmc1 register. if this mechanism is enabled, the fifo will enter a fifo lock state at the detection of the eom criterion. during the time that the fifo is locked, it is not possible to receive additional data in run mode self polling. this means that it is only possible to detect another wake-up in the self polling mode, but no more data in the run mode self polling. this will guarantee that only the first complete data packet is stored in the fifo. enabling fifolk also locks the digital receive chain at eom until release from fifo lock state. the fifo will remain locked unless one of three conditions occurs: 1.) the remaining contents of the fifo are completely read out via the spi 2.) the sfr control bit fifolk is cleared 3.) initfifo at cycle start is set in the cmc1 register and a) fsm is switched to run mode slave or b) fsm switches from self polling mode to run mode self polling figure 54 fifo lock behavior wait till fifo is empty write data into fifo fifo lock eom=0 initfifo (init fifo@ cycle start) = 1 accept data fifo empty=1 fifolk=0 eom=1 fifolk=1 eom=1 fifolk=0 fifo empty = 0 fifolk=1 TDA5235 functional description data sheet 84 v1.0, 2010-02-19 fifo status word the fifo status word is attached at the end of a fifo spi transmission, and shows if there was an overflow, and how many valid data bits were transmitted. the number of valid fifo bits is indicated at bit positions s0 to s5. s6 of the status word is always undefined. figure 55 spi data fifo read if the write address pointer outruns the read address pointer, an overflow is indicated in the fifo overflow status bit in the fifo read status word at position s7. all 32 fifo bits and the bits s5 to s0 of the status word are undefined while the overflow status bit is set. if a tsi is detected after an overflow, the fifo overflow status bit is cleared and the entire receive fifo is initialized. initialization additionally, there are two possibilities to initialize the receive fifo. ? if the initfifo bit is set in the cmc1 register (?init fifo at cycle start?) the entire receive fifo is always initialized a.) after switching to run mode slave or b.) switching from self polling mode to run mode self polling. ? if the fsinitfifo bit in cmc1 register is set, the entire receive fifo is initialized when a tsi is detected and the receive fifo is not locked (?init fifo at frame start?). last received message length for application protocols with several payload frames and only a short pause in- between, the microcontroller would have to read out the fifo very fast after detection of an eom. thus even slow or overloaded application controllers have the possibility now to determine the end of the last message, when reading out the fifo, while the next payload frame gets already received and payload data is further stored in the fifo. 32 fifo bits sdi sdo high impedance z d0 d1 d30 d31 i7 i6 i1 i0 s7 s6 s1 s0 status word data sheet 85 v1.0, 2010-02-19 TDA5235 functional description therefore the last received message length (e.g. after an eom event) is stored in register pldlen and the upper two bits of register rfpllacc at tsi detection of the next message. the upper two bits of register rfpllacc hold the msbs, thus a message length of 256 up to 1023 payload bits can be depicted. a saturation of the message length at the maximum value of 1023 is realized. storage at tsi of the next message ensures that even wrong payload data (e.g. if mid is not matching, no eom will be generated, but payload is kept in fifo. or eom data length criterion is selected only and a sync loss prevents from generating an eom event) can be identified. on initialization of the fifo, the register pldlen and the upper two bits of register rfpllacc are cleared. the corresponding internal counter is cleared with every tsi detection and initialization of the fifo. pldlen will work correctly in case: (initdrxes = 0) and ( (data rate > 22kbit/s) or (eom2spm = 0) ) if the condition above is not fulfilled, then the chip internal state machine can set pldlen to 0 and a correct function of pldlen cannot be guaranteed. 2.5.3 digital output pins as long as the p_on pin is high, all digital output pins operate as described. if the p_on pin is low, all digital output pins are switched to high impedance mode. the digital outputs pp0, pp1, pp2 and pp3 are configurable, where each of the signals clk_out, rx_run, nint, a low level (gnd) and a high level, data, data_matchfil, ch_data, ch_str, rxd and rxstr can be routed to any of the four output pins. there is only one exception, clk_out is not available on pp3. the default configuration for these four output pins can be seen in table 1 . each port pin can be inverted by usage of ppcfg2 register. the rx_run signal is active high for all configurations by default. it can be deactivated for every configuration separately. every ppx can be configured with an individual rx_run setup. this can be set in rxruncfg0 and rxruncfg1 registers. interfacing to 3.3v logic: the TDA5235 is able to interface directly to a 3.3v logic, when chip is operated in 3.3v environment. interfacing to 5v logic: the TDA5235 is able to interface directly to a 5v logic, when chip is operated in 5v environment. TDA5235 functional description data sheet 86 v1.0, 2010-02-19 emc reduction of digital i/os: because electromagnetic distortion generated by digital i/os may interfere with the high sensitivity radio receiver, it is recommended that all inputs are filtered by adding an rc low pass circuit. 2.5.4 interrupt generation unit the TDA5235 is able to signal interrupts (nint signal) to the external application controller on one of the ppx port pins (for further details see chapter 2.5.3 digital output pins ). the interrupt generation unit receives all possible interrupts and sets the nint signal based on the configuration of the interrupt mask register im0. the interrupt status register is0 is set from the interrupt generation unit, depending on which interrupt occurred. the polarity of the interrupt can be changed in the ppcfg2 register. please note that during power up and brownout reset, the polarity of nint signal is always as described in chapter 2.4.9.2 chip reset . a reset event has the highest priority. it sets all bits in the status register to ?1? and sets the interrupt signal to ?0?. the first interrupt after the reset event will clear the status register and will set the interrupt signal to ?1?, even if this interrupt is masked. a wake-up interrupt clears the fsynca, fsyncb and the complementary wake-up flag. an fsync interrupt clears the eoma, eomb, mida, midb and the complementary fsync flag. the interrupt status register is always cleared after read out via spi. it is not possible to disable the power on reset indicator interrupt using the interrupt mask register. some interrupts are not usable depending on the selected receive mode, which is described in chapter 2.5.1.2 data interface . interrupts for wu can be used in all receive modes. interrupts for fsync, mid and eom can only be used in the receive modes potp and pof. data sheet 87 v1.0, 2010-02-19 TDA5235 functional description figure 56 interrupt generation unit figure 57 interrupt generation waveform (example for configuration a+b) is0 interrupt-mask interrupt-signalling im0 wake-up cfg a eom cfg a message id cfg a fsync cfg a wake-up cfg b eom cfg b message id cfg b fsync cfg b power-up / brownout reset eomb wub fsyncb midb eo m a wua fsynca mida nint nint signal pp2_select=nint fsync(a,b) reset wu(a,b) mid(a,b) eom(a,b) pp2(nint) pp2inv is0 x ff 01 03 07 0f 1c 30 70 f0 spi read is0 00 configb configa TDA5235 functional description data sheet 88 v1.0, 2010-02-19 the following handling mechanism for read-clear registers was chosen due to implementation of the burst read command: ? the current interrupt status (isx) register 8-bit content is latched into the spi shift register after the last address bit is clocked-in ( point a in figure 58 ) ? the is register is then cleared after last is register bit is clocked out of the spi interface ( point b in figure 58 ) consequence: any interrupt event occurring in the window-time between points a and b is cleared at point b and not stored/shown in an later readout of isx. (however: nint signal is toggling in any case, if occurring interrupt is not masked in imx register) figure 58 isx readout set clear collision please see also the important note in the burst read section ! ncs inst addr read /readb data = is(t+0) read/capture is * content sfr is* read clear @end of data frame nint irq1 (masked?) irq2 (masked?) sfr is* is(t+0) is(t+1) 0x00 is(t-1) note: sfr is(j) status flag is cleared before it can be read if an irq occurs during spi data frame spi if 8-bit @2mhz = 4us a b data sheet 89 v1.0, 2010-02-19 TDA5235 functional description 2.5.5 digital contro l (4-wire spi bus) the control interface used for device control and data transmission is a 4-wire spi interface. ? ncs - select input, active low ? sdi - data input ? sdo - data output ? sck - clock input: data bits on sdi are read in at rising sck edges and written out on sdo at falling sck edges. level definition: logic 0 = low voltage level logic 1 = high voltage level note for non-burst modes: it is possible to send multiple frames while the device is selected. it is also possible to change the access mode while the device is selected by sending a different instruction. note: in all bus transfers msb is sent first, except for the received data read from the fifo. there the bit order is given as first bit received is first bit transferred via the bus. to read from the device , the spi master has to select the spi slave unit first. therefore, the master must set the ncs line to low. after this, the instruction byte and the address byte are shifted in on sdi and stored in the internal instruction and address register. the data byte at this address is then shifted out on sdo . after completing the read operation, the master sets the ncs line to high. figure 59 read register data out sdi sdo high impedance z sck ncs d7 d6 d5 d4 instruction i7 i6 i3 i2 register address i1 i0 frame i5 i4 a7 a6 a3 a2 a1 a0 a5 a4 d3 d2 d1 d7 d6 d5 d4 instruction regist er address d3 d2 d1 d0 data out frame 181818181818 d0 i7 i6 i3 i2 i1 i0 i5 i 4 a7 a6 a3 a2 a1 a0 a5 a4 TDA5235 functional description data sheet 90 v1.0, 2010-02-19 to read from the device in burst mode , the spi master has to select the spi slave unit first. therefore the master has to drive the ncs line to low. after the instruction byte and the start address byte have been transferred to the spi slave (msb first), the slave unit will respond by transferring the register contents beginning from the given start address (msb first). driving the ncs line to high will end the burst frame. figure 60 burst read registers important note - for being upwards compatible with further versions of the product, we give following strong recommendation: for read-clear registers at address (n), no read-burst access stopping at address (n-1) is allowed, because read-clear register will be cleared without being read out. use single read command to read out the register at address (n-1) or extend the burst read to include the read-clear register at address (n). to write to the device, the spi master has to select the spi slave unit first. therefore, the master must set the ncs line to low. after this, the instruction byte and the address byte are shifted in on sdi and stored in the internal instruction and address register. the following data byte is then stored at this address. after completing the writing operation, the master sets the ncs line to high. additionally the received address byte is stored into the register spiat and the received data byte is stored into the register spidt . these two trace registers are readable. therefore, an external controller is able to check the correct address and data transmission by reading out these two registers after each write instruction. the trace registers are updated at every write instruction, so only the last transmission can be checked by a read out of these two registers. data out (i) sdi sdo high impedance z sck ncs d7 d6 d5 d4 instruction i7 i6 i3 i2 register start address i1 i0 i5 i4 a7 a6 a3 a 2 a1 a0 a5 a4 d3 d2 d1 d7 d6 d5 d4 d3 d2 d1 d0 data out (i+x) 181818 18 d0 d7 d6 d5 d4 d3 d2 d1 d0 data out (i+1) 18 d7 d0 data sheet 91 v1.0, 2010-02-19 TDA5235 functional description figure 61 write register to write to the device in burst mode , the spi master has to select the spi slave unit first. therefore the master has to drive the ncs line to low. after the instruction byte and the start address byte have been transferred to the spi slave (msb first) the successive data bytes will be stored into the automatically addressed registers. to verify the spi burst write transfer, the current address (start address, start address + 1, etc.) is stored in register spiat and the current data field of the frame is stored in register spidt. at the end of the burst write frame the latest address as well as the latest data field can be read out to verify the transfer. note that some error in one of the intermediate data bytes can not be detected by reading spidt. driving the ncs line to high will end the burst frame. a single spi burst write command can be applied very efficiently for data transfer either within a register block of configuration dependent registers or within the block of configuration independent registers. figure 62 burst write registers sdi sdo high impedance z sck ncs instruction frame 18 i7 i6 i3 i2 i1 i0 i5 i4 d7 d6 d5 d4 d1 d0 d3 d2 regist er address 18 data byte 18 instruction frame 18 register address 18 data byte 18 a7 a6 a3 a2 a1 a0 a5 a4 i7 i6 i3 i2 i1 i0 i5 i4 d7 d6 d5 d4 d1 d0 d3 d2 a7 a6 a3 a2 a1 a0 a5 a4 sdi sdo high impedance z sck ncs instruction 18 i7 i6 i3 i2 i1 i0 i5 i4 d7 d6 d5 d4 d1 d0 d3 d 2 register start address 18 data byte (i) 18 data byte (i+1) 18 data byte (i+x) 18 a7 a6 a3 a2 a1 a0 a5 a4 d7 d6 d5 d4 d1 d0 d3 d2 d7 d6 d3 d2 d1 d0 d5 d 4 TDA5235 functional description data sheet 92 v1.0, 2010-02-19 the spi also includes a safety feature by which the checksum is calculated with an xor operation from the address and the data when writing sfr registers. the checksum is in fact an xor of the data 8-bitwise after every 8 bits of the spi write command. the calculated checksum value is automatically written in the spichksum register and can be compared with the expected value. after the spichksum register is read, its value is cleared. in case of an spi burst write frame, a checksum is calculated from the spi start address and consecutive data fields. figure 63 spi checksum generation to read the fifo, the spi master has to select the spi slave unit first. therefore, the master must set the ncs line to low. after this, the instruction byte is shifted in on sdi and stored in the internal instruction register. the data bits of the fifo are then shifted out on sdo . the following byte is a status word that contains the number of valid bits in the data packet. after completing the read operation, the master sets the ncs line to high. figure 64 read fifo table 4 instruction set instruction description instruction format wr write to chip 0000 0010 rd read from chip 0000 0011 rdf read fifo from chip 0000 0100 wrb write to chip in burst mode 0000 0001 rdb read from chip in burst mode 0000 0101 spi shift register xor checksum sfr read/clear enable every 8 bit 32 fifo bits sdi sdo high impedance z sck ncs d0 d1 d30 d31 instruction i7 i6 i1 i0 s7 s6 s1 s0 status word instruction i7 i6 i1 i0 32 fifo bits d0 d1 d30 d31 s7 s6 s1 s0 st at us word frame frame 18132181813218 data sheet 93 v1.0, 2010-02-19 TDA5235 functional description 2.5.5.1 timing diagrams figure 65 serial input timing figure 66 serial output timing ncs sdi t sdi_hold t sdi_ se tu p t not_hold t n o t_ se tu p t hold sdo high impedance z t de se le ct sck t cl k_ h t cl k_ l t se tu p z sdo sdi z addr lsb ncs sck t cl k_ sdo t sdo_disable t sdo _ r t sdo _ f t cl k_ h t cl k_ l t cl k_ sdo TDA5235 functional description data sheet 94 v1.0, 2010-02-19 2.5.6 chip serial number every device contains a unique, preprogrammed 32-bit wide serial number. this number can be read out from sn3, sn2, sn1 and sn0 registers via the spi interface. the TDA5235 always has sn0.6 set to 1 and sn0.5 set to 0. figure 67 chip serial number table 5 spi bus timing parameter symbol parameter f clock clock frequency t clk_h clock high time t clk_l clock low time t setup active setup time t not_setup not active setup time t hold active hold time t not_hold not active hold time t deselect deselect time t sdi_setup sdi setup time t sdi_hold sdi hold time t clk_sdo clock low to sdo valid t sdo_r sdo rise time t sdo_f sdo fall time t sdo_disable sdo disable time fuses ...... fuse- readout- interface sn0 sn1 sn2 ...... sn3 data sheet 95 v1.0, 2010-02-19 TDA5235 functional description 2.6 system management unit (smu) the system management unit consists of two main units: ? master control unit , where the various operating modes can be configured. ? polling timer unit , where the receiver?s on and off times and modes are defined. the polling timer unit is only working in the self polling mode. 2.6.1 master control unit (mcu) 2.6.1.1 overview the master control unit controls the operation modes, the global states, and is generally responsible for automating data reception, verification, identification, extraction, and storage into the fifo. the payload data without runin, tsi and optional eom can be read from the fifo via spi by the external microcontroller. alternatively, a transparent data stream can also be processed externally by the application controller (see chapter 2.5.1.2 data interface ). the following operation modes and the behavior of the master control unit are fully automatic and only influenced by sfr settings and by incoming rf data streams. the TDA5235 has two major operation modes, which are switched by sfr bit msel. in slave mode the device is controlled via spi by the external microcontroller. this mode supports: ? run mode slave (rms) , where the receiver is continuously active ? sleep mode , where the receiver is switched off for power saving. this mode can also be used to change register settings ? hold mode , allows register settings to be changed. the change to hold mode and back to rms is faster than changing to sleep mode and back to rms. in slave mode, switching between configurations, as well as between run and sleep mode must be initiated by the microcontroller. in self polling mode, TDA5235 autonomously polls for incoming rf signals. the receiver switches automatically between up to two configurations (configuration a and b). further information can be found in chapter 2.6.2 . between the rf signal scans, the receiver is automatically switched to low power mode for reducing the average power consumption. if an incoming signal fulfills the selected wake-up criterion an interrupt can be generated and run mode self polling will be entered. if the following received data matches to the tsi pattern, and passes the optional message id screening, the payload is loaded into the fifo, and, if not masked, an interrupt is generated. then the payload data can be read via spi. TDA5235 functional description data sheet 96 v1.0, 2010-02-19 figure 68 global state diagram 2.6.1.2 run mode slave (rms) in run mode slave, the receiver is able to continuously scan for incoming data streams. detection and validation of a wake-up cr iterion are not performed, but runin and tsi are required. recognition of tsi and validation of the optional mid (message identification) are done automatically. the data payload is extracted from the data stream, and moved to the fifo. the various recognition steps are communicated by interrupts. interrupts can be generated at frame-start (when a valid tsi has been detected), when a valid mid has been found and at eom (end of message). alternatively, a transparent data stream can also be processed externally by the application controller (see chapter 2.5.1.2 data interface ). run mode slave is entered by setting sfr cmc0 bits msel to 0 and slrxen to 1. sleep mode chip is idle init initialize rx-part run mode slave chip is permanently active bit:slrxen == 1 bit:msel == 0 init self polling mode bit:slrxen == 0 or bit:msel == 1 bit:slrxen == 1 bit:msel == 0 bit:slrxen == 0 bit:msel == 0 bit:slrxen == x bit:msel == 1 bit:slrxen == x bit:msel == 0 chip is periodically active and searching for wu criteria run mode self polling bit:slrxen == x bit:msel == 0 totim timeout == x bit:slrxen == x bit:msel == 1 wuc found == 0 bit:slrxen == 1 bit:msel == 0 bit :slrxen == x bit :msel == 1 bit:slrxen == x bit:msel == 1 wuc found == 1 chip is permanently active initialize rx-part reset bit:slrxen == x bit:msel == 1 totim timeout == 0 bit:slrxen == x bit:msel == 1 totim timeout == 1 bit:slrxen == x bit:msel == 0 bit:slrxen == 0 or bit:msel == 1 bit:slrxen == x bit:msel == 1 eom2spm == 1 data sheet 97 v1.0, 2010-02-19 TDA5235 functional description configurations are switched via sfr bit mcs in the cmc0 register. the rf channel can be selected by sfrs x_pllintc1, x_pllfrac0c1, x_pllfrac1c1, x_pllfrac2c1, where x = a or b. the configuration may be changed only in sleep or in hold mode before returning to the previously selected operation mode. this is necessary to restart the state machine with defined settings at a defined state. otherwise the state machine may hang up. reconfigurations in hold mode are faster, because there is no start-up sequence. the following flowchart and explanation show and help to understand the internal behavior of the finite state machine (fsm) in run mode slave. TDA5235 functional description data sheet 98 v1.0, 2010-02-19 figure 69 run mode slave check mid setup check the mid setup register wait wait till symbol synchronization is found wait init mid scanning unit initialize the mid scanning unit mid screening enable == 1 wait till frame start is found symbol sync == 0 frame sync == 0 frame sync == 1 extproc==00 symbol sync == 1 extproc<>10 wait store rx data into fifo wait for scan finish mid scanning finished == 0 mid scanning finished == 1 checking id scanning result store rx data into fifo analyze the scanning result symbol sync ==0 initdrxes==1 mid found == 0 eom check store rx data into fifo check for eom mid screening enable == 0 eom found == 1 mid found=1 generating a frame start interrupt if not masked generating a mid found interrupt if not masked generating a eom interrupt if not masked startup finished == 0 wait wait till startup has finished startup finished == 1 eom found == 0 fifo locked wait till fifo read out fifolk == 1 extproc==00 fifolk == 0 fifolk == 1 init fifo init fifo = init fifo@fsync init init fifo=init fifo@cyc. 0 1 4 3 5 6 7 8 9 10 11 hold ready for reconfiguration 12 hold == 1 hold == 0 fifolk == 0 initdrxes==0 init init digital receiver symbol sync ==0 initdrxes==0 2 fifolk == 0 initdrxes==1 data sheet 99 v1.0, 2010-02-19 TDA5235 functional description 2.6.1.3 hold mode this state (item 12 in figure 69 ) is used for fast reconfiguration of the chip in run mode slave. this state can be reached after the start-up sequencer and initialization of the chip have been completed from any state from 3 to 11. to reconfigure the chip the sfr control bit hold must be set. after reconfiguration in this state the sfr control bit hold must be cleared again. after leaving the hold state, the init state is entered and the receiver can work with the new settings. be aware that the time between changing the configuration and reinitialization of the chip has to be at least 40us. take note that one spi command for clearing the sfr control bit hold needs 24 bits or 12 s at an spi data rate of 2.0mbit/s. the remaining 28 s must be guaranteed by the application. figure 70 hold state behavior (initpllhold disabled) in case of large frequency steps, an additional vac routine (vco automatic calibration) has to be activated when recovering from hold mode (initpllhold bit). the maximum allowed frequency step in hold mode without activation of vac routine is depending on the selected frequency band. the limits are +/- 1 mhz for the 315 mhz band, +/- 1.5 mhz for the 434 mhz band and +/- 3 mhz for the 868/915 mhz band. when this additional vac routine is enabled, the TDA5235 starts initialization of the digital receiver block after release from hold and an additional channel hop time. figure 71 hold state behavior (initpllhold enabled) hold mode is only available in run mode slave. configuration changes in self polling mode have to be done by switching to sleep mode and returning to self polling mode after reconfiguration. eom-check fsm state address cmc0 instruction wr i te 0x02 data hold=1 spi command instruction wr i te 0x02 address x_pll... data (sel. other channel) address cmc0 instruction wr i te 0x02 data hold=0 hold init wait till ssync 12 us @ 2. 0m hz 40 us eom-check fsm state address cmc0 instruction wr ite 0x02 data hold=1 spi command instruction wr ite 0x02 address x_pll... data (sel. other channel) address cmc0 instruction wr ite 0x 0 2 data hold=0 hold init wait till ssync 12 us @ 2. 0m hz 40us t c_hop vac vac TDA5235 functional description data sheet 100 v1.0, 2010-02-19 2.6.1.4 sleep mode the sleep mode is a power save mode. the complete rf part is switched off and the oscillator is in low power mode. as in hold mode, the chip can be reconfigured. when switching from sleep to run mode slave, the state machine starts with the internal start-up sequence. 2.6.1.5 self polling mode (spm) in self polling mode TDA5235 autonomously polls for incoming rf wake-up data streams. there is no processing load on the host microcontroller. when a wake-up criterion has been found, an interrupt can be generated and the TDA5235 mode is changed to run mode self polling for automatic verification of tsi, optional mids and for transfer of payload data into the fifo. a general overview on a typically transmitted protocol and the behaviour of the TDA5235 is given in figure 72 . figure 72 spm - tx-rx interaction alternatively, a transparent data stream can also be processed externally by the application controller (see chapter 2.5.1.2 data interface ). self polling mode is entered by setting the msel register bit to 1. configuration changes are allowed only by switching to sleep mode, and returning to self polling mode after reconfiguration. (runin) tsi payload tx - rx interaction in rx - self polling mode tx telegram: eom runin + wake-up sequence data frame wake-up frame wake-up frame continued or gap 1) rx mode: run mode self polling legend: 1) there can either be a wake -up frame directly followed by a data frame or the wake -up frame is separated from the data f rame by a gap in -between . 2) the position of the o n time can vary ( a , b , ...) as there is no synchronization between transmitted telegram and start of the receiver?s on time. on time 2) self polling mode on time 2) self polling mode a b data sheet 101 v1.0, 2010-02-19 TDA5235 functional description the polling timer unit controls the timing for scanning (on time) and sleeping (off time, spm_off). up to two independent configuration sets (a and b) can automatically be processed, thus enabling scanning from different transmit sources. see also chapter 2.6.2 polling timer unit . the wake-up generation unit identifies, whether an incoming data stream matches the configurable wake-up criterion. after fulfillment of the wake-up criterion, modulation can be switched automatically. see also chapter 2.6.1.6 automatic modulation switching , chapter 2.4.8.5 wake- up generator and chapter 2.5.1.2 data interface (in subsection tmrds). the following state diagrams and explanations help to illustrate the behavior during self polling mode. first there is a search for a wake-up criterion according to configuration a. then, there is an optional search for a wake-up criterion according to configuration b. in applications using only single-configuration, settings are always taken from configuration a. TDA5235 functional description data sheet 102 v1.0, 2010-02-19 figure 73 wake-up search with configuration a idle chip is idle startup finished == 0 wait wait till startup has finished startup finished == 1 wu search cfg a ffts search for a configurated wake up criteria fast fall back init with cfg a initialize rx- part configuration a wu search finished == 0 modulation switching cfg a modulation selection depending on register setting rx_run=0 compare compare loop counter against number of configs wu search finished == 1 wu found == 0 store channel store the current channel configuration into actual channel register init loop counter cfgloopcounter is initialized cfgloopcounter <> cfgnr rx_run == 0 rx_run == 1 to init loop counter of config b from compare of config b cfgloopcounter == cfgnr wu search finished == 1 wu found == 1 generating wu cfg a interrupt if not masked wu search with configuration a from run mode self polling wu search cfg a coot search for a configurated wake up criteria const on off const on time on time elapsed == 0 wu found == 0 on time elapsed == x wu found == 1 on time elapsed == 1 wu found == 0 permanent wu search mode enable == 1 permanent wu search mode enable == 0 permanent wu search mode enable == 1 permanent wu search mode enable == 0 fast fall back to sleep 1 2 3 4 5 7 7 9 8 run mode self polling chip is permanently active 12 data sheet 103 v1.0, 2010-02-19 TDA5235 functional description figure 74 wake-up search with configuration b init with cfg b initialize rx-part configuration b modulation switching cfg b modulation selection depending on register setting run mode self polling chip is permanently active from compare of config a to init loop counter / idle of config a wu search with configuration b wu search cfg b ffts search for a configurated wake up criteria fast fall back wu search finished == 0 compare compare loop counter against number of configs wu search finished == 1 wu found == 0 store channel store the current channel configuration into actual channel register (cfgloopcounter == cfgnr) wu search finished == 1 wu found == 1 generating wu cfg b interrupt if not masked wu search cfg b coot search for a configurated wake up criteria const on off on time elapsed == 0 wu found == 0 on time elapsed == x wu found == 1 on time elapsed == 1 wu found == 0 const on time permanent wu search mode enable == 1 permanent wu search mode enable == 0 fast fall back to sleep 4 5 7 7 9 8 12 TDA5235 functional description data sheet 104 v1.0, 2010-02-19 2.6.1.6 automatic modulation switching in self polling mode , the chip is able to automatically change the type of modulation after a wake-up criterion was fulfilled in a received data stream. the type of modulation used in the different operational modes is selected by the sfr control bit mt. 2.6.1.7 multi-cha nnel in self polling mode a simple multi-channel behavior can be realized when the same application parameters are programmed in both configuration sets and only the rf pll frequency differs. channel frequencies are defined in registers x_pllintc1, x_pllfrac0c1, x_pllfrac1c1, x_pllfrac2c1, where x = a or b. see also chapter 2.4.5 sigma-delta fractional-n pll block . 2.6.1.8 run mode self polling (rmsp) the chip enters run mode self polling after a successful fulfillment of a wake-up criterion in self polling mode. when wake-up criterion for rssi or signal recognition (see chapter 2.4.8.1 ) is selected and fulfilled, this leads to a change to run mode self polling . this will be interesting especially in case of a transparent data stream being processed externally by the application controller (see chapter 2.5.1.2 data interface ). the following steps are performed automatically, depending on register settings: ? modulation switching (see chapter 2.6.1.6 automatic modulation switching ) ? wait for valid tsi (see chapter 2.4.8.6 frame synchronization ) ? initialize fifo (see chapter 2.5.2 receive fifo ) and write data to fifo ? scan for mids (see chapter 2.4.8.7 message id scanning ) depending on interrupt masking, the host microcontroller is alerted when ? a data frame has started, ? an mid has been found, (if enabled) or ? eom (end of message) has been detected. see also chapter 2.5.4 interrupt generation unit run mode self polling is left, when synchronization is lost and the timeout timer for loss of synchronization (totim_sync) has elapsed, or when one of the other timeout timers (totim_tsi, totim_eom) for each configuration (a, b) has elapsed, or when an eom occurred and the sfr bit eom2spm is activated, or when the operating mode is switched to sleep or run mode slave by the host microcontroller. data sheet 105 v1.0, 2010-02-19 TDA5235 functional description timeout timers for getting no tsi or getting no eom within a certain time period can be used to avoid a deadlock situation, e.g. totim_tsi can be used in case an interfering transmit signal fulfilled the wake-up criterion and keeps on transmitting, but no tsi can be found in this data stream within a certain programmable time period. totim_eom might be used in case eom criterion ?eom by payload data length? cannot be applied. the timeout timer functionality in the absence/presence of an interfering signal is shown in figure 75 and figure 76 . figure 75 totim behavior without presence of interferer tx signal runmode selfpolling selfpolling / sleep wu-data interrupt totim_sync counter activity totim_eom counter activity rx_run init totims totim_tsi counter activity without interfering signal: wu frame and payload frame have the same modulation type e.g. totim_tsi is set to 15ms wake-up ri tsi payload1 eom ri tsi payload2 eom 9.5ms 5ms 5ms TDA5235 functional description data sheet 106 v1.0, 2010-02-19 figure 76 totim behavior in presence of interferer on expiring of one of the timeout timers, the receiver proceeds with self polling mode and with searching for a suitable wake-up criterion on the next configuration or a search for a wake-up criterion in configuration a is initiated. as long as the chip is in run mode self polling, incoming data frames (including a runin sequence and tsi, but without necessity of additional wake-up patterns) can be received and stored. the data fifo can be initialized and cleared either at ? cycle start, that means whenever run mode self polling is entered or ? frame start, when a tsi has been successfully identified (and receive fifo is not locked). further information about the receive fifo can be found in the chapter 2.5.2 receive fifo . after an eom was found, the information about the rf channel and the configuration of the actual payload data is saved in the rfpllacc register. eo m tx signal runmode selfpolling selfpolling / sleep wu-data interrupt totim_sync counter activity totim_eom counter activity rx_run init totims totim_tsi counter activity with interfering signal (interferer signal has same data rate as wanted wake-up signal): wu frame and payload frame have the same modulation type e.g. totim_tsi is set to 15ms wake-up ri tsi payload1 ri tsi payload2 eo m 15ms tx interferer *) *) chip proceeds with self po lling mode data sheet 107 v1.0, 2010-02-19 TDA5235 functional description after detection of eom the TDA5235 can either proceed with a search for a wake-up criterion in the next configuration or a search for wake-up in configuration a can follow or the totims of the current configuration are reloaded for being prepared to receive another (redundant) payload data frame within the same configuration. alternatively, a transparent data stream can also be processed externally by the application controller. therefore the external controller needs the possibility to send following commands, which would normally be generated by the TDA5235 itself (see figure 77 and extpcmd register as well): ? exttotim: so the TDA5235 can proceed with self polling mode (either with the next configuration or with configuration a). ? exteom found: in this case the TDA5235 can either proceed with self polling mode (either with the next configuration or with configuration a) or stay in run mode self polling. exttotim and exteom are only available, when the external processing mode is deactivating functional blocks (see bit group x_chcfg.extproc). when the actual processed configuration is right before the off time and the application controller sends one of the above mentioned commands, then the TDA5235 can proceed with the off time (in case next configuration is selected). if the autonomous wake-up search with configuration a follows a totim or eom event, then also the polling timer is initialized, this means a new on period is started. in case the wake-up search gets started with next configuration (after a totim or eom event), then the polling timer is not initialized. this means that the on time counter proceeds with the old value from leaving the previous wake-up search period successfully. this is the case for fast fall back to sleep mode. in constant on-off time mode the polling timer is always initialized after a totim or eom event. TDA5235 functional description data sheet 108 v1.0, 2010-02-19 figure 77 run mode self polling extproc==00 fifolk == 1 exttotim (from external controller ) check mid setup check the mid setup register wait start totim timer sync (if enabled) modulation selection depending on register setting wait init mid scanning unit initialize the mid scanning unit mid screening enable == 1 start totim tsi (if enabl.) wait till frame start is found modulation switching all operations are done with the wake up configuration wait store rx data into fifo wait for scan finish mid scanning finished == 0 mid scanning finished == 1 checking id scanning result store rx data into fifo analyze the scanning result symbol sync ==0 initdrxes==0 mid found == 0 eom check store rx data into fifo check for eom pwuf = pwuen bit mid screening enable == 0 eom found == 1 mid found == 1 generating a frame start interrupt if not masked generating a mid found interrupt if not masked generating a eom interrupt if not masked totim timeout sync == 1 symbol sync == x extproc <> 10 totim timeout sync == 0 symbol sync == 0 to self polling mode (wu search with next configuration ) it is possible to disable the timeout feature fifo locked wait till fifo read out totim timeout sync == 0 symbol sync == 1 extproc <> 10 totim timeout sync == 1 symbol sync == x totim timeout tsi == 0 frame sync == 1 extproc==00 init fifo start totimeom (if enab.) init fifo= initfifo@fsync init if pwuf == 0 then { init fifo = init fifo@cycle start } pwuf = 0 0 1 4 3 5 7 8 9 10 11 6 totim timeout tsi == 0 frame sync == 0 totim timeout tsi == 1 frame sync == x extproc == 00 totim timeout eom == 1 eom found == x totim timeout eom == 0 eom found == 0 goto next config after eom to self polling mode (wu search with next configuration) eom 2ncfg == 1 14 eom2ncfg == 0 goto selfpolling after eom 13 eom 2spm == 0 eom 2spm == 1 to self polling mode (wu search with configuration a) goto sp next configuration 15 totim2nch == 1 to self polling mode (wu search with configuration a ) totim2nch == 0 totim timeout == 1 exteom found (from external controller ) init totims initialize totim timers 2 fifolk == 0 save channel and configuration information 12 totim timeout eom == 1 parallel wake-up found 16 wu found == 1 pwuf == 1 wu found == 1 pwuf == 1 generating wu cfg x interrupt if not masked init if initfrcs == 1 then init framer 1.1 init init digital receiver 17 initdrxes==0 initdrxes==1 init init digital receiver 3.1 fifolk == 0 symbol sync ==0 initdrxes==1 data sheet 109 v1.0, 2010-02-19 TDA5235 functional description while the TDA5235 is in run mode self polling, further wake-ups would normally not be detected by the receiver. if the functionality of a parallel wake-up search during the search for a tsi is desired, this can be activated by the pwuen bit. in this case the wake-up search is not active during a recognized payload and is only active after the first received payload frame, as can be seen from figure 77 . this feature can only be used, when modulation type is the same for spm and rmsp. so after a reception of the eom from the current payload, the parallel wu search can take place in this mode. the wu search will be active after symbol sync has been detected. the wu search will be active until the synchronization gets lost or wake-up is generated. after the synchronization gets lost the wu search will be finished and wake- up can not be detected any more (the tsi search continues as usual). following procedure can be applied with help of 3 spi write command sequences. the idea is to generate external eom every time the symbol sync goes to inactive state and no interrupt (tsi or wu) has been detected. this will bring the mcu to the cycle start and reinitialize the wu search. configuration: write x_wuc.pwuen = 1 // enable parallel wake-up search write x_wurssith1 0xff // set rssi threshold to max value (avoid wu during the reinitialization procedure) write x_wulot 0xff // set wulot to max value (avoid wu during the reinitialization procedure) TDA5235 functional description data sheet 110 v1.0, 2010-02-19 figure 78 parallel wake-up search notes: - symbol sync can be activated on any ppx port pp0: write 0xf4 0x07 & write ppcfg0 0x0e pp1: write 0xf4 0x70 & write ppcfg0 0xe0 pp2: write 0xf5 0x01 & write ppcfg1 0x0e pp3: write 0xf5 0x10 & write ppcfg1 0xe0 - symbol sync monitoring necessary only in run mode between frames and wu pattern or till software timeout generated wait for wake-up interrupt wu irq wait for tsi interrupt tsi irq wait for eom interrupt eom irq wait for interrupt wait for sw timeout tsi irq sw timeout symbol sync = 0 wait for symbol sync (on ppx) (if no isr impl.) symbol sync = 1 wu irq interrupt activate symbol sync on ppx (example for pp 0; for other ppx see notes below ) write 0xf 4 0x07 write ppcfg0.pp0cfg = 0xe deactivate symbol sync on ppx (example for pp0 = rx_run) write ppcfg0.pp0cfg = 0x1 only necessary if other ppx signals needed during self -polling otherwise configure ppx once at the beginning 1. force symbol sync for mcu to 0 write 0xed 0x40 2. select external processing (for ext. eom) write x_chcfg.extproc = 0x2 3. generate external eom write extpcmd 0x01 4. disable external processing write x_chcfg.extproc = 0x0 5. unforce symbol sync write 0xed 0x00 timeout -> sleep -> spm or (dependent on application ) ext_totim : * select external processing (for ext. totim ) ( write x_chcfg.extroc = 0x2) * generate external totim (write extpcmd 0x02) * disable external processing ( write x_chcfg.extroc = 0x0) eom generation - must be faster than runin duration data sheet 111 v1.0, 2010-02-19 TDA5235 functional description - generation of external eom will reinitialize also the totim timers - external eom generation period should be smaller than the runin length (7 chips runin = ~62 us @ 112 kchip/s , 5 spi write commands = ~ 60 us @ 2 mbit) - minimal symbol sync active period = tvwin, minimal symbol sync inactive period = runin for protocols where no ask/fsk switching is required between the wake-up and payload frame, the wake-up and tsi pattern can share the same bits (e.g. wake-up pattern = ..00000, tsi = 000001, all bits manchester encoded). this function can be activated by the initfrcs bit, so then there is no reset of the framer compare shift register after a wake-up event, which can shorten the required processing time. TDA5235 functional description data sheet 112 v1.0, 2010-02-19 2.6.2 polling timer unit figure 79 polling timer unit the polling timer unit consists of a counter stage and a control fsm (finite state machine). the counter stage is divided into three sub-modules. the reference timer is used to divide the state machine clock (f sys /64) into the slower clock required for the spm timers. the on-off timer and the active idle period timer are used to generate the polling signal. the entire unit is controlled by the spm fsm. the TDA5235 is able to handle up to two different sets of configurations automatically. self-polling-mode (spm) fsm spm reference-timer (8 bit) spm on -off-timer (14 bit) spm active-idle period timer (5 / 8 bit) polling mode spmrt spmofft0 spmofft1 spmap spmip f onoff f sys / 64 f rt timer-control timer-control timer-control timer-status timer-status spmc receiver-enable to master-control-unit no wu spmontx0 spmontx1 data sheet 113 v1.0, 2010-02-19 TDA5235 functional description 2.6.2.1 self polling modes four polling modes are available to fit the polling behavior to the expected wake-up patterns and to optimize power consumption in self polling mode. the following 4 polling modes are available and can be configured via 2 bits in the configuration register spmc: ? constant on-off (coo) ? fast fall back to sleep (ffb) ? mixed mode (mm) ? permanent wake-up search (pwus) a detected wake-up data sequence or an actual value for rssi or signal recognition (a combination of signal detector and noise detector, see chapter 2.4.8.1 ) exceeding a certain adjustable threshold forces the TDA5235 into run mode self polling. in all modes the timing resolution is defined by the reference timer, which scales the incoming frequency (f sys /64) corresponding to the value, which is defined in the self polling mode reference timer (spmrt) register. changing values of spmrt helps to fit the final on-off timing to the calculated ideal timing. 2.6.2.2 constant on-off time (coo) in this mode there is a constant on and a constant off time. therefore also the resulting master period time is constant. the on and off time are set in the spmonta0, spmonta1, spmontb0, spmontb1, spmofft0 and spmofft1 registers. the on time configuration is done separately for configuration a and b. when single-configuration is selected then only configuration a is used. multi- configuration mode allows reception of up to 2 different transmit sources. the diagram below shows possible scenarios. all receive modes described in chapter 2.5.1.2 data interface can be used. TDA5235 functional description data sheet 114 v1.0, 2010-02-19 figure 80 constant on-off time calculation of the on time: the on time must be long enough to ensure proper detection of a specified wake-up criterion. therefore the on time depends on the wake-up pattern, and the wake-up criterion. it has to include transmitter data rate tolerances. a widely used wake-up pattern is a sequence of equal bi-phase encoded bits or a certain bi-phase encoded bit pattern. t on also must include the relevant start-up times. in case of the first configuration after t off , this is the receiver start-up time. in case of the following configuration b (rf receiver is already on, there is only a change of the configuration), e.g. if configuration b is used, this is the configuration change latency time. in addition, it has to be considered that some data bits are required for synchronization and internal latency, see chapter 2.4.8.8 runin, synchronization search time and inter-frame time . there are other wake-up patterns in use as well, which have several (up to 10 and more) short wake-up sequences (a few byte each) that are separated by a certain pause (again a few byte each). in this case the on time has to be set, so that a possible wake-up can be found within two wake-up sequences including the pause in-between. calculation of the off time: the longer the off time, the lower the average power consumption in self polling mode. on the other hand, the off time has to be short enough that no transmitted wake-up a t aon t off t masterperiod single config multi config a t aon t off t masterperiod b t bon t m aster per iod = t aon + t off t m aster per iod = t aon + t bon + t off rx polling run mode sleep m ode rx polling run mode sleep m ode data sheet 115 v1.0, 2010-02-19 TDA5235 functional description pattern is missed. therefore the off time depends mainly on the duration of the expected wake-up pattern. for basic timing of wu on rssi in coo mode, please see figure 81 . figure 81 coo polling in wu on rssi mode always check at the end of the current observation time window, if there is a wu (wake- up) event or not. this means, in algorithmic description (see also figure 10 , chapter 2.4.7 rssi peak detector and chapter 2.4.8.5 wake-up generator ): if (rssipwu_value > x_wurssith1) and (rssipwu_value > x_wurssibh1) then wu else not here, ?not? means to keep on evaluating and move on to the next observation time window, also keep on peak value tracking of rssipwu signal. keep on walking through the observation time windows until there is a wu event from the algorithm above or finally decide at the end of the on time with the following algorithm: if (rssipwu_value > x_wurssith1) and (rssipwu_value < x_wurssibl1 or rssipwu_value > x_wurssibh1) then wu else not if there is a wu event at the end of an observation time window while walking through the observation time windows, freeze/hold this decision/peak value in register rssipwu for optional read out and switch to run mode self polling. instead of the single rssi criterion also the signal recognition criterion can be activated. rf signal e. g . ask rx on sleep t startup t on t t t wulot t wulot 12 t wulot t wulot_part n-1 n partially last observation time window is forced to end by end of t on latest decision here ! TDA5235 functional description data sheet 116 v1.0, 2010-02-19 combined level and data criterion in coo mode on using the wake-up on data criterion in coo mode, the rssi criterion (including the rssi blocking window) can be applied additionally by setting the bit x_wuc.uffblcoo. this means that a wake-up interrupt will not be generated, when a blocking rssi level (e.g. an interfering signal) is detected even when the data criterion is fulfilled. the behavior of the additional rssi criterion is similar to the behavior in ultrafast fall back mode. after the level observation time the receiver checks, if the rssi level is within a valid range. if rssi is within a valid range, the state machine will go on to check the data criterion. if the rssi is within a forbidden range, a new level observation time is started (note that no parts of the wake-up pattern are lost in this case, when the rssi criterion succeeds within the following observation time). this will be done as long as the rssi value is within a forbidden range and the on time is not elapsed. if the receiver loses synchronization within the search for the data criterion (e.g. pattern detection), the wu unit will be initialized and checks again for the rssi criterion. instead of the additional rssi criterion also signal recognition criterion can be applied. when the signal recognition threshold (x_wurssibh1) is not exceeded at observation time, the wake-up on level fsm (finite state machine) and wake-up on data fsm are initialized. if the threshold is exceeded, then the wake-up on level fsm enters the ready state and has no further impact on wake-up search until the wake-up unit is initialized again. when afterwards a data criterion is found to be ok (e.g. pattern matches, number of equal bits or random bits is reached), the wake-up search is completed positively. when a data criterion is found to be not ok, the wake-up search is terminated independent of the state of the wake-up on level fsm. therefore both fsms are initialized. data sheet 117 v1.0, 2010-02-19 TDA5235 functional description 2.6.2.3 fast fall back to sleep (ffb) this mode is used to switch off the receiver, if there is no rf signal, as quickly as possible to reduce power consumption. during the search for wake-up data, there is a check for a bit stream, to which the system can be synchronized. if there is no synchronization to a bit stream within the so-called sync search time out (sysrcto), the wake-up search for this channel is stopped. if synchronization to a bit stream is possible (and not lost again), the TDA5235 waits if the wake-up criterion is fulfilled. if the wake-up criterion is not fulfilled (in worst case, if the last bit of an expected wake-up data pattern is wrong), the wake-up procedure for this configuration is stopped, and the TDA5235 tries to synchronize on the next configuration, or falls back to sleep. that means that the effective search time and, consequently, the receiver active time is significantly shorter, and power consumption is reduced, when no input signal is present. calculation of sync search time out can be found in chapter 2.4.8.8 runin, synchronizat ion search time and inter-frame time . the needed time for detecting that no relevant transmission took place can be further reduced by using ultrafast fall back to sleep (uffb). when there was no wake-up on level criterion fulfilled in uffb mode during the observation time (t wulot , see chapter 2.4.8.5 ), then the system goes back to sleep (or to next config). this can further reduce the receiver active time, when no data is available. when wake-up on level criterion was fulfilled, then the system proceeds with normal ffb functionality (sysrcto, optional wake-up data criterion). note: uffb and ffb start working at the same time! ultrafast fall back to sleep is working, when a wake-up on data criterion is selected, the uffblcoo bit is enabled and ffb or pwus mode is selected. the uffb level criterion can be selected in the x_wuc register. figure 82 ultrafast fall back to sleep rf signal e.g. ask rx on sleep t startup t sysrcto t wu-data-pattern t wulot uffb ffb ffb t on t t TDA5235 functional description data sheet 118 v1.0, 2010-02-19 at the end of the observation time the rssi peak tracking value of rssipwu signal is compared to the 3 thresholds. then the decision is made. the algorithmic description is as follows (see also figure 10 , chapter 2.4.7 rssi peak detector and chapter 2.4.8.5 wake-up generator ): if (rssipwu_value > x_wurssith1) and (rssipwu_value < x_wurssibl1 or rssipwu_value > x_wurssibh1) then wu else not instead of the rssi criterion also signal recognition criterion can be applied. when the signal recognition threshold (x_wurssibh1) is not exceeded at observation time, then the system goes back to sleep or the wake-up on level fsm (finite state machine) is initialized and a wake-up search is performed on the next specified configuration. figure 83 uffb activation wake-up generation fsm wucrt wu criterion pattern equal bits random bits sync signal recognition rssi wu on level criterion wu on data criterion wucrt (2) wucrt (1) wucrt (0) & & ffb is selected & 4 5 3 1 2 0 0 1 wulcuffb uffb criterion uffblcoo data sheet 119 v1.0, 2010-02-19 TDA5235 functional description the on and off time setting is different from the constant on-off time mode. the entire on time is defined in the spmonta0 and spmonta1 registers. regardless of the numbers of configurations, the on time is defined with the configuration a on-timer. the deactivation of the receiver can happen at different times, but this event does not influence the timer stage, because the on time is still the same. so the master period is constant. the following scenarios are the same as before, but with fast fall back to sleep. only the following receive modes (see chapter 2.5.1.2 data interface ) can be used: ? packet oriented fifo mode (pof) ? packet oriented transparent payload mode (potp) ? transparent mode - chip data and strobe (tmcds) figure 84 fast fall back to sleep calculation of the on time: the on time, which is now a sum for all of the configurations used, must include enough time to ensure proper detection of the specified wake-up pattern on all configurations. to cover the worst case scenario, the maximum time is required on all configurations as in constant on-off. t on must also include the relevant start-up times. in case of the first configuration after t off , this is the receiver start-up time. in case of the following configuration b (rf receiver is already on, there is only a change of the configuration), e.g. if configuration b is used, this is the configuration change latency time. t aon t off t m aster per iod single config multi config t aon t off t masterperiod t masterperiod = t aon + t off t masterperiod = t aon + t off rx polling run mode sleep mode rx polling sleep mode a a b run mode TDA5235 functional description data sheet 120 v1.0, 2010-02-19 in addition, it has to be considered that some data bits are required for synchronization and internal latency (see chapter 2.4.8.8 runin, synchronization search time and inter-frame time ). calculation of the off time: the same general rules apply as for constant on-off time. the off time has to be short enough that no wake-up pattern reception is missed. 2.6.2.4 mixed mode (mm, const on-off & fast fall back to sleep) this mode combines constant-on time and fast fall back to sleep within different configuration sets: cfg.a: coo; cfg.b: ffb t on for configuration a is always calculated according to const on-off rules. t on for configuration b is always calculated according to fast fall back to sleep rules. in mixed mode the on time of configuration b is used for the ffb group. below there are shown the same scenarios as before, but now for mixed mode. note that single- configuration can be set, but is not recommended in mixed mode. only the following receive modes (see chapter 2.5.1.2 data interface ) can be used: ? packet oriented fifo mode (pof) ? packet oriented transparent payload mode (potp) ? transparent mode - chip data and strobe (tmcds) figure 85 mixed mode a t aon t off t m aster period single config multi config a t aon t off t masterperiod b t masterperiod = t aon + t bon + t off t masterperiod = t aon + t bon + t off t bon t bon rx polling run mode sleep mode rx polling run mode sleep mode data sheet 121 v1.0, 2010-02-19 TDA5235 functional description 2.6.2.5 permanent wake-up search (pwus) in this mode the receiver will work in fast fall back mode, but it will not go back to the sleep state after the last configuration has been searched. instead, it will start again from the beginning (configuration a) until the on time has elapsed. the timing calculation can be seen in figure 86 . ultrafast fall back to sleep functionality can be used as well. only the following receive modes (see chapter 2.5.1.2 data interface ) can be used: ? packet oriented fifo mode (pof) ? packet oriented transparent payload mode (potp) ? transparent mode - chip data and strobe (tmcds) figure 86 permanent wake-up search a b t ao n t off t m aster per iod single config multi config t aon t off t m aster per iod b t master per iod = t aon + t off t masterperiod = t ao n + t off a a rx polling r un mode sleep mode rx polling r un mode sleep mode a a a a a a TDA5235 functional description data sheet 122 v1.0, 2010-02-19 2.6.2.6 active idle period selection this mode is used to deactivate some polling periods and can additionally be applied to each of the above mentioned polling modes. normally, polling starts again after the t masterperiod . with this active idle period selection some of the polling periods can be deactivated, independent from the polling mode. the active and the idle sequence is set with the spmap and the spmip registers. the values of these registers determine the factor m and n. figure 87 active idle period sleep mode rx polling run mode t on t off t masterperiod n*t masterperiod m*t masterperiod active idle data sheet 123 v1.0, 2010-02-19 TDA5235 functional description 2.7 definitions 2.7.1 definition of bit rate the definition for the bit rate in the following description is: if a symbol contains n chips (for manchester n=2; for nrz n=1) the chip rate is n times the bit rate: 2.7.2 definition of manchester duty cycle several different definitions for the manchester duty cycle (mdc) are in place. to avoid wrong interpretation some of the definitions are given below. figure 88 definition a: level-based definition this definition determinates the duty cycle to be the ratio of the high pulse width and the ideal symbol period. the dc content is constant and directly proportional to the specified duty cycle. for t > 0 the high period is longer than the chip-period and for t < 0 the high period is shorter than the chip-period. bitrate symbols s --------------------- - = chiprate n bitrate = level-based definition mdc = duration of h-level / symbol period bit = 1 0 0 1 1 1. chip 2. chip t bit t c h i p mdc < 50% 1 0 0 1 1 t bit t h t bit t h t c h i p t mdc > 50% t bit t h t bit t h t c h i p t TDA5235 functional description data sheet 124 v1.0, 2010-02-19 depending on the bit content, the same type of edge (e.g. rising edge) is sometimes shifted and sometimes not. with this definition the manchester duty cycle is calculated to figure 89 definition b: chip-based definition this definition determinates the duty cycle to be the ratio of the first symbol chip and the ideal symbol period independently of the information bit content. the dc content depends on the information bit and it is balanced only if the message itself is balanced. for t > 0 the first chip-period is longer than the ideal chip-period and for t < 0 the first chip-period is shorter than the ideal chip-period. depending on the bit content, the same type of edge (e.g. rising edge) is sometimes shifted and sometimes not. mdc a t h t bit --------- t chip t + t bit -------------------------- - == bit = 1 0 0 1 1 1. chip 2. chip t bit t c h i p chip-based definition mdc = duration of the first chip / symbol period mdc < 50% 1 0 0 1 1 mdc > 50% t bit t 1.chip t c h i p t t bit t 1.chip t bit t 1.chip t bit t 1.chip t c h i p t data sheet 125 v1.0, 2010-02-19 TDA5235 functional description with this definition the manchester duty cycle is calculated to figure 90 definition c: edge delay definition this definition determinates the duty cycle to be the ratio of the duration of the delayed high-chip and the ideal symbol period independently of the information bit content. the position of the high-chip is determined by the delayed rising edge and/or the delayed falling edge. for t = t fall -t rise the manchester duty cycle is calculated to independent on the bit content, the same type of edge (rising edge and/or falling edge) is shifted. mdc b t 1.chip t bit ---------------- t chip t + t bit -------------------------- == bit = 1 0 0 1 1 1. chip 2. chip t bit t c h i p edge delay definition mdc = duration delayed edge / symbol period 1 0 0 1 1 mdc < 50% t f = 0 t c h i p t t bit t h t bit t r t h 1 0 0 1 1 mdc > 50% t r = 0 t c h i p t t bit t bit t f t h t f t bit t h t bit t r mdc c t delayedhighchip t bit ---------------------------------------- t chip t + t bit -------------------------- t chip t fall t rise ? + t bit ----------------------------------------------- - === TDA5235 functional description data sheet 126 v1.0, 2010-02-19 2.7.3 definition of power level the reference plane for the power level is the input of the receiver board. this means, the power level at this point (p r ) is corrected for all offsets in the signal path (e.g. attenuation of cables, power combiners etc.). the specification value of power levels in terms of sensitivity is related to the peak power of p r in case of on-off keying (ook). this is noted by the unit dbm peak. specification value of power levels is related to a manchester encoded signal with a manchester duty cycle of 50% in case of ask modulation. an rf signal generator usually displays the level of the unmodulated carrier (p carrier ). this has following consequences for the different modulation types: for power levels in sensitivity parameters given as average power, this is noted by the unit dbm. peak power can be calculated by adding 3 db to the average power level in case of ask modulation and a manchester duty cycle of 50%. 2.7.4 symbols of sfr registers and control bits figure 91 sfr symbols table 6 power level modulation scheme realization with rf signal generator power level specification value ask am 100% p r = p carrier + 6db ask pulse modulation (=ook) p r = p carrier fsk fm with deviation f: f 1 = f carrier - f f 2 = f carrier + f p r = p carrier symbolizes unique sfr registers or sfr control bit(s), which are common for all configuration sets . control control symbolizes sfr registers or sfr control bit(s) with multi-configuration capability (protocol specific). in case of sfr register, the name starts with a _ or b_, depending on the selected configuration. this is generally noted by the prefix ?x _?. data sheet 127 v1.0, 2010-02-19 TDA5235 functional description 2.8 digital control (sfr registers) 2.8.1 sfr address paging an spi instruction allows a maximum address space of 8 bit. the address space for supporting more than one configuration set is exceeding this 8 bit address room. therefore a page switch is introduced, which can be applied via register sfrpage (see figure 92 ). figure 92 sfr address paging 2.8.2 sfr register list and detailed sfr description the register list is attached in the appendix at the end of the document. registers for configuration b are equivalent and not shown in detail. all registers with prefix ?a_? are related to configuration a. all these registers are also available for configuration b having the prefix ?b_?. logical address space 0x000 0x 0f f 0x100 0x180 0x 1f f physical address space 384 d d d 255 256 d 511 d 0 1) configuration dependent register block (2 protocol specific sets) page switch via sfrpage register 2), 4) reserved ? forbidden area 3) configuration independent registers (common for all configurations ) map (?mirror? ) to the same physical address space 0x080 d 128 common registers 3) reserved 4) common registers 3) reserved 4) configuration b 1) - page 1 reserved 2) configuration b 1) - page 1 reserved 2) common registers 3) reserved 4) configuration a 1) - page 0 reserved 2) configuration a 1) - page 0 reserved 2) TDA5235 functional description data sheet 128 v1.0, 2010-02-19 data sheet 129 v1.0, 2010-02-19 TDA5235 applications 3 applications figure 93 typical application schematic note: as a good practice in any rf design, shielding around sensitive nodes can improve the emc performance of the application. for achieving the best sensitivity results the following has to be kept in mind. every digital system generates certain frequencies (f src , e.g. the crystal frequency or a microcontroller clock) and harmonics (n * f src ) of it, which can act as interferer (emi source) and therefore sensitivity can be reduced. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ifbuf_in ifbuf_o ut gnda ifmix_ inp ifmix_ inn vdd 5v vdd d vdd d1 v5 gndd pp0 pp1 pp2 p_on xt al1 if_out vdda rssi pp3 gndrf lna_inp lna_inn t2 t1 sdo sdi sck ncs xtal2 TDA5235 saw filter rf in if cer filter (opt.) if cer filter (opt.) vs vs spi bus to/from c to c TDA5235 applications data sheet 130 v1.0, 2010-02-19 there are two different cases, which need to be checked for the desired receive channel(s): elimination of in-band emi mixing with (2*m + 1) * f lo , where m > 0: a square wave is used as lo (local oscillator) for the switching-type mixer, which also has odd harmonics. when the harmonics of the emi source are exactly the if frequency away from the harmonics of the lo, these spurs will be down-converted to the if frequency and act as a co-channel interferer within the receiver?s channel bandwidth mainly in the 315 mhz band. in this case a change of the lo injection side (high side or low side injection) can be applied. example (low side lo-injection): wanted channel f rf = 314.233mhz ==> f lo = 303.533mhz ==> 3*f lo = 910.599mhz f xosc = 21.948717 mhz ==> 41 * f xosc = 899.8974 mhz resulting if = 910.599 - 899.8974 mhz = 10.702 mhz ==> co-channel interferer within the receiver?s channel bandwidth ==> change lo injection side example (high side lo-injection): wanted channel f rf = 314.233 mhz ==> f lo = 324.933 mhz ==> 3*f lo = 974.799 mhz f xosc = 21.948717 mhz ==> 44 * f xosc = 965.744 mhz; 45 * f xosc = 987.692 mhz ==> both xosc harmonics are not generating a co-channel interferer at 10.7 mhz a final sensitivity measurement on the application hardware is recommended. elimination of in-band emi mixing with 1 * f lo : assuming a harmonic (n * f src ) is falling within the bw of the wanted channel and has an impact on the sensitivity there. in this case another xtal frequency shall be selected, e.g. 10 khz away | n * f src - f localoscillator | < bw channel example (e.g. emi source TDA5235 xosc): f xosc = 21.948717 mhz ==> 42 * f xosc = 921.846114 mhz for further details please refer to the corresponding application note or to the latest configuration software. 3.1 configuration example please see configuration files supplied with the explorer tool. data sheet 131 v1.0, 2010-02-19 TDA5235 reference 4 reference 4.1 electrical data 4.1.1 absolute maximum ratings attention: the maximum ratings must not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the ic may result. table 7 absolute maximum ratings # parameter symbol limit values unit remarks min. max. a1 supply voltage at vdd5v pin v smax -0.3 +6 v a2 supply voltage at vddd, vdda pin v smax -0.3 +4 v a3 voltage between vdd5v vs vddd and vdd5v vs vdda v smax -0.3 +4 v a4 junction temperature t j -40 +125 c a5 storage temperature t s -40 +150 c a6 thermal resistance junction to air r th(ja) 140 k/w a7 total power dissipation at t amb = 105c p tot 100 mw a8 esd hbm integrity v hbmrf -2 2 kv according to esd standard jedec eia / jesd22-a114-b a9 esd sdm integrity (all pins except corner pins) v sdm -500 500 v a10 esd sdm integrity (all corner pins) v sdm -750 750 v a11 latch up i lu 100 ma aec-q100 (transient current) a12 maximum input voltage at digital input pins v inmax -0.3 v dd5v +0.5 or 6.0 v whichever is lower a13 maximum current into digital input and output pins i iomax 4ma TDA5235 reference data sheet 132 v1.0, 2010-02-19 4.1.2 operating range table 8 supply operating range and ambient temperature # parameter symbol limit values unit remarks min. max. b1 supply voltage at pin vdd5v v dd5v 4.5 5.5 v supply voltage range 1 b2 supply voltage at pin vdd5v=vddd=vdda v dd3v3 3.0 3.6 v supply voltage range 2 b3 ambient temperature t amb -40 105 c data sheet 133 v1.0, 2010-02-19 TDA5235 reference 4.1.3 ac/dc characteristics supply voltage vdd5v = 4.5 to 5.5 volt or vdd5v = vdda = vddd = 3.0 to 3.6 volt ambient temperature t amb = -40...105 o c; t amb = +25 o c and vdd5v = 5.0v or vdd5v = vdda = vddd = 3.3v for typical parameters, unless otherwise specified. not subject to production test - verified by characterization/design table 9 ac/dc characteristics # parameter symbol limit values unit test conditions remarks min. typ. max. general dc characteristics c1.1 supply current in run mode and double down conversion mode i run, double 12 15 ma ask or fsk mode p in < -50dbm c1.2 supply current in run mode and single down conversion mode i run, single 10.5 14 ma ask or fsk mode p in < -50dbm c2 supply current in sleep mode i sleep_low crystal oscillator in low power mode; clock generator off; valid for sleep mode and during spm off time t amb = 25 c 40 50 a t amb = 85 c 60 110 a t amb = 105 c 90 160 a c3 supply current in sleep mode i sleep_high 115 350 a crystal oscillator in high precision mode c load = 25 pf; clock generator off; valid for sleep mode and during spm off time c4 supply current in power down mode i pdn t amb = 25 c 0.8 1.5 a t amb = 85 c 3.7 13 a t amb = 105 c 9.0 27 a c5 supply current clock generator i clock 23 27 a f clockout = 1 khz c load = 10 pf c6 supply current if-buffer i buffer 0.5 0.7 ma f if_1 = 10.7 mhz r load = 330 no ac signal TDA5235 reference data sheet 134 v1.0, 2010-02-19 c7 supply current during rf-fe startup / bpf calibration i rf-fe- startup,bpfcal 2.2 2.9 ma c8 brownout detector threshold v bor 2.3 2.45 2.6 v c9 receiver reset time t reset 1.0 3.0 ms note: no spi communication is allowed before xosc start-up is finished and chip reset is already finished c10 receiver startup time t rxstartup 455 455 455 s time to startup rf frontend (comprises time required to switch crystal oscillator from low power mode to high precision mode c11 rf channel hop latency time and configuration (hop) change latency time (e.g. cfg a to cfg b) t c_hop 111 111 111 s time to switch rf pll between different rf channels (does not include settling of data clock recovery) and time to change configuration c12 rf frontend startup delay t rfstartdelay 350 350 350 s delay of startup of rf frontend c13 p_on pulse width t p_on 15 s minimal pulse width to reset the chip c14 nint pulse length t nint_pulse 12 s pulse width of interrupt c15 accuracy of temperature sensor valid for temperature range -40c .. +105c; using upper 8 adc bits (adcresh) c15.1 uncalibrated t error, uncal +/- 23 c uncalibrated (3 sigma) value c15.2 calibrated t error, cal +/- 4.5 c after 1-point calibration at room temperature (3 sigma) c16 accuracy of vddd readout valid for temperature range -40c .. +105c; using upper 8 adc bits (adcresh) c16.1 uncalibrated v ddd, error, uncal +/- 200 mv uncalibrated (3 sigma) value c16.2 calibrated v ddd, error, cal +/- 25 mv after 1-point calibration at room temperature (3 sigma) # parameter symbol limit values unit test conditions remarks min. typ. max. data sheet 135 v1.0, 2010-02-19 TDA5235 reference general rf characteristics (overall) d1 frequency range 1 f band_1 300 320 mhz 1 st local oscillator low side lo-injection and high side lo- injection allowed; see also chapter 3 range 2 f band_2 425 450 mhz range 3 f band_3 863 870 mhz range 4 f band_4 902 928 mhz d2 frequency step of sigma-delta pll f step 10.5 hz f step = f xtal / 2 21 d3 ask demodulation data rate r data 0.5 40 kchip/s data rate tol. r data_tol -10 +10 % modulation index m ask 50 100 % ask m ook 99 100 % on-off keying d4 fsk demodulation data rate r data 0.5 112 kchip/s including tolerance data rate tol. r data_tol -10 +10 % frequency deviation f 1 64 khz frequency deviation zero-peak modulation index m fsk 1.0 m = frequency_ deviation zero-peak / maximum_occuring_data _frequency; m >= 1.25 is recommended at small frequency deviation d5 decoding schemes manchester, differential manchester, bi-phase mark / bi-phase space duty cycle ask t chip / t data 35 55 % see chapter 2.7.2 definition c duty cycle fsk t chip / t data 45 55 % see chapter 2.7.2 definition b d6 overall noise figure rf input matched to 50 @ t amb = 25 c noise figure nf 6 8 db # parameter symbol limit values unit test conditions remarks min. typ. max. TDA5235 reference data sheet 136 v1.0, 2010-02-19 d7 ber sensitivity (fsk) ber = 2*10 -3 rf input matched to 50 @ t amb = 25 c; single-ended matching without saw; insertion loss of input matching network = 1db; receive mode = tmmf (sampled with ideal data clock); double down conversion manchester coding; for additional test conditions see right after this table d7.1 data rate 2 kbit/s; f = 10 khz sfsk1 ber -119 -116 dbm 2 nd if bw = 50 khz pdf = 33 khz, afc off, ifatt=0 d7.2 data rate 10 kbit/s; f = 14 khz sfsk2 ber -114 -111 dbm 2 nd if bw = 50 khz pdf = 65 khz, afc off, ifatt=0 d7.3 data rate 10 kbit/s; f = 50 khz sfsk3 ber -112 -109 dbm 2 nd if bw = 125 khz pdf = 132 khz, afc off, ifatt=0 d7.4 data rate 50 kbit/s; f = 50 khz sfsk4 ber -105 -102 dbm 2 nd if bw = 300 khz pdf = 239 khz, afc off, ifatt=0 d7.5 data rate 2 kbit/s; f = 10 khz sfsk5 ber -110 -107 dbm 2 nd if bw = 300 khz pdf = 282 khz, ifatt=7 note: 3db sensitivity loss @ f offset =+/-90khz @ afc on d7.6 data rate 10 kbit/s; f = 14 khz sfsk6 ber -106 -103 dbm 2 nd if bw = 300 khz pdf = 282 khz, ifatt=7 note: 3db sensitivity loss @ f offset =+/-90khz @ afc on d7.7 data rate 10 kbit/s; f = 50 khz sfsk7 ber -110 -107 dbm 2 nd if bw = 300 khz pdf = 282 khz, ifatt=7 note: 3db sensitivity loss @ f offset =+/-90khz @ afc on # parameter symbol limit values unit test conditions remarks min. typ. max. data sheet 137 v1.0, 2010-02-19 TDA5235 reference d8 ber sensitivity (ook) ber = 2*10 -3 rf input matched to 50 @ t amb = 25 c, peak power level (see chapter 2.7.3 ); single-ended matching without saw; insertion loss of input matching network = 1db; receive mode = tmmf (sampled with ideal data clock); double down conversion manchester coding; for additional test conditions see right after this table d8.1 data rate 0.5 kbit/s sask1 ber -120 -117 dbm peak m = 100%, ifatt=0 2 nd if bw = 50 khz d8.2 data rate 2 kbit/s sask2 ber -116 -113 dbm peak m = 100%, ifatt=0 2 nd if bw = 50 khz d8.3 data rate 10 kbit/s sask3 ber -111 -108 dbm peak m = 100%, ifatt=0 2 nd if bw = 50 khz d8.4 data rate 16 kbit/s sask4 ber -109 -106 dbm peak m = 100%, ifatt=0 2 nd if bw = 80 khz d8.5 data rate 0.5 kbit/s sask5 ber -115 -112 dbm peak m = 100%, ifatt=7 2 nd if bw = 300 khz; note: 3db sensitivity loss @ f offset = +/-100 khz d8.6 data rate 2 kbit/s sask6 ber -112 -109 dbm peak m = 100%, ifatt=7 2 nd if bw = 300 khz; note: 3db sensitivity loss @ f offset = +/-100 khz d8.7 data rate 10 kbit/s sask7 ber -106 -103 dbm peak m = 100%, ifatt=7 2 nd if bw = 300 khz; note: 3db sensitivity loss @ f offset = +/-100 khz d8.8 data rate 16 kbit/s sask8 ber -104 -101 dbm peak m = 100%, ifatt=7 2 nd if bw = 300 khz; note: 3db sensitivity loss @ f offset = +/-100 khz d9.1 sensitivity increase for single down conversion mode s sdc 00.51 db d9.2 double down conversion sensitivity decrease for higher blocking performance (ifatt=0 => ifatt=7) s ddc, ifatt7 12 db # parameter symbol limit values unit test conditions remarks min. typ. max. TDA5235 reference data sheet 138 v1.0, 2010-02-19 d9.3 single down conversion sensitivity decrease for higher blocking performance (ifatt=4 => ifatt=7) s sdc, ifatt7 0.5 1 db d10.1 sensitivity variation due to temperature (-40...+105c) p in 2 db relative to t amb = 25 c; temperature drift of crystal not considered d10.2 sensitivity variation due to frequency offset 1) p in 3 db afc inactive; for sensitivity bandwidth see table 11 d10.3 sensitivity variation due to frequency offset p in 3 db afc active, slow afc; for sensitivity bandwidth see table 11 and applied afclimit d10.4 sensitivity loss when afc active at center frequency p in 1 db afc active; center frequency - no afc wander (see chapter 2.4.6.3 ) d11 3 rd order intercept iip3 p iip3 -16 -14 dbm input matched to 50 ; insertion loss of input matching network = 1db; ifatt = 7; valid for single and double down conversion mode d12 1 db compression point cp1db p cp1db -27 -25 dbm input matched to 50 ; insertion loss of input matching network = 1db; ifatt = 7; valid for single and double down conversion mode d13 1 st if image rejection d image1 30 40 db 1 st if = 10.7 mhz without front end saw filter; valid for double down conversion mode d14 2 nd if image rejection d image2 30 34 db 2 nd if = 274 khz without 1 st if cer filter; valid for single and double down conversion mode # parameter symbol limit values unit test conditions remarks min. typ. max. data sheet 139 v1.0, 2010-02-19 TDA5235 reference rf front end characteristics (unless otherwise noted, all values apply for the specified frequency ranges) e1 lna input impedance e1.1 f rf = 315 mhz r in_p,diff 680 differential parallel equivalent input between lna_inp and lna_inn c in_p,diff 1.05 pf e1.2 f rf = 434mhz r in_p,diff 570 c in_p,diff 0.87 pf e1.3 f rf = 868mhz r in_p,diff 550 c in_p,diff 0.63 pf e1.4 f rf = 915mhz r in_p,diff 540 c in_p,diff 0.63 pf e1.5 f rf = 315 mhz r in_p, se 500 single-ended parallel equivalent input between lna_inp and gndrf / lna_inn and gndrf c in_p, se 1.87 pf e1.6 f rf = 434mhz r in_p, se 400 c in_p, se 1.63 pf e1.7 f rf = 868mhz r in_p, se 322 c in_p, se 1.59 pf e1.8 f rf = 915mhz r in_p, se 312 c in_p, se 1.56 pf e2 fe output impedance r out_if 290 330 380 f if = 10.7 mhz e3 fe voltage conversion gain av fe, max 34 36 38 db min. if attenuation (ifatt = 0); input matched to 50 ; insertion loss of input matching network = 1db r load_if = 330 ; tested at 434 mhz e4 fe voltage conversion gain av fe_7 29 31 33 db if attenuation (ifatt = 7); input matched to 50 ; insertion loss of input matching network = 1db r load_if = 330 ; tested at 434 mhz # parameter symbol limit values unit test conditions remarks min. typ. max. TDA5235 reference data sheet 140 v1.0, 2010-02-19 e5 fe voltage conversion gain av fe, min 22 24 26 db max. if attenuation (ifatt = 15); input matched to 50 ; insertion loss of input matching network = 1db r load_if = 330 ; tested at 434 mhz e6 fe voltage conversion gain step 0.8 db 12db / 15 = 0.8db/step double down conversion: 16 gain settings (4 bit) single down conversion: 7 gain settings e7 1 st local oscillator ssb noise closed loop e7.1 pll loop bandwidth bw 100 150 200 khz bw and its tolerances e7.2 f in_r1 = 315mhz d ssb_lo -81 -76 dbc/hz @ f offset = 1 khz -85 -80 @ f offset = 10 khz -82 -77 @ f offset = 100 khz -120 -115 @ f offset = 1 mhz -130 -125 @ f offset => 10 mhz e7.3 f in_r2 = 434mhz d ssb_lo -78 -73 dbc/hz @ f offset = 1 khz -83 -78 @ f offset = 10 khz -82 -77 @ f offset = 100 khz -117 -112 @ f offset = 1 mhz -130 -125 @ f offset => 10 mhz e7.4 f in_r3 = 868mhz d ssb_lo -75 -70 dbc/hz @ f offset = 1 khz -79 -74 @ f offset = 10 khz -77 -72 @ f offset = 100 khz -114 -109 @ f offset = 1 mhz -130 -125 @ f offset => 10 mhz e7.5 f in_r4 = 915mhz d ssb_lo -71 -66 dbc/hz @ f offset = 1 khz -79 -74 @ f offset = 10 khz -77 -72 @ f offset = 100 khz -116 -111 @ f offset = 1 mhz -130 -125 @ f offset => 10 mhz e8.1 spurious emission < 1 ghz -57 dbm e8.2 spurious emission > 1 ghz -47 dbm # parameter symbol limit values unit test conditions remarks min. typ. max. data sheet 141 v1.0, 2010-02-19 TDA5235 reference e9 inband fractional spur -40 dbc e10 3db overall analog frontend bandwidth bw ana 230 khz lna input to limiter output, excluding external cer filter 1 st if buffer characteristics f1 input impedance r in_if 290 330 370 f if = 10...12 mhz f2 output impedance r out_if 290 330 370 f if = 10...12 mhz f3 voltage gain av buffer 345 dbf if = 10...12 mhz z source = 330 z load = 330 f4 buffer switch isolation (cerfsel) d isolation 60 db f if = 10...12 mhz see figure 6 2 nd if mixer, rssi and filter characteristics g1 mixer input impedance r in_if 290 330 390 f if = 10...12 mhz g2 rssi related to rf input matched to 50 g2.1 dynamic range (linearity +/- 2 db) dr rssi -110 -30 dbm applies for digital rssi; agc on -115 -60 dbm applies for analog rssi @ 50khz bpf, agc off -110 -50 dbm applies for analog rssi @ 300khz bpf, agc off g2.2 linearity dr lin -1 +1 db -95 dbm...-35 dbm; applies for digital rssi g2.3 temperature drift within linear dynamic range dr temp -2.5 +1.5 db -95 dbm...-35 dbm; applies for digital rssi g2.4 output dynamic range v rssi+ 0.8 2.0 v g2.5 analog rssi error, untrimmed drssi ana -4 +2 db at rssi pin g2.6 analog rssi slope, untrimmed dv rssi / dv mix_in 8 10 12 mv/db at rssi pin; typical 600 mv/60 db = 10 mv/db g2.7 digital rssi error, untrimmed drssi dig_u -4 +2 db rssi register readout # parameter symbol limit values unit test conditions remarks min. typ. max. TDA5235 reference data sheet 142 v1.0, 2010-02-19 g2.8 digital rssi error, user trimmed via sfrs rssislope and rssioffs drssi dig_t -1 +1 db rssi register readout g2.9 digital rssi slope, untrimmed dv rssi / dv mix_in 22.53 lsb /db rssi register readout; typical 600 mv/60 db = 10 mv/db, 1mv = 1 lsb (10-bit adc) 8-bit readout: 4mv=1lsb g2.10 digital rssi slope, user trimmed via sfrs rssislope and rssioffs dv rssi / dv mix_in 2.35 2.5 2.65 lsb /db rssi register readout; typical 600 mv/60 db = 10 mv/db, 1mv = 1 lsb (10-bit adc) 8-bit readout: 4mv=1lsb g2.11 resistive load at rssi pin r l,rssimax 100 k g2.12 capacitive load at rssi pin c l,rssi 20 pf g3 2nd if filter (3rd order bandpass filter) g3.1 center frequency f center 262 274 288 khz asymmetric bpf corners: f_center=sqrt(f low * f high ); use afc for more symmetry g3.2 -3 db bw bw -3db 50 80 125 200 300 khz g3.3 -3 db bw tolerance tol_bw -3db -5 +5 % for bw = 125, 200, 300 khz g3.4 -3 db bw tolerance tol_bw -3db -6 +6 % for bw = 50, 80 khz # parameter symbol limit values unit test conditions remarks min. typ. max. data sheet 143 v1.0, 2010-02-19 TDA5235 reference crystal oscillator characteristics h1 frequency range f xtal 21.948 717 mhz h2 crystal parameters h2.1 motional capacitance c 1 3610ff h2.2 motional resistance r 1 18 80 h2.3 shunt capacitance c 0 24 pf h2.4 load capacitance c load 12 pf nominal value h2.5 initial frequency tolerance f xtal_tol -30 +30 ppm oscillator untrimmed (trim capacitor default settings, usage of recommended crystal); not including crystal tolerances h2.6 frequency trimming range f xtal -50 +50 ppm larger trimming range possible via sd pll h2.7 trimming step f x_step 1 4 ppm see also step size of sd pll h3 clock output frequency at ppx pin f clock_out 11 5.5m hz 10pf load h4 crystal oscillator settling time (switching from low power to high precision mode) t coscsettle 292 292 292 s h5 start up time t start_up 0.45 1 ms crystal type: ndk nx5032sd; see also bom for ext. load caps; note: no spi communication is allowed before xosc start-up is finished and chip reset is already finished # parameter symbol limit values unit test conditions remarks min. typ. max. TDA5235 reference data sheet 144 v1.0, 2010-02-19 digital inputs/outputs characteristics i1 high level input voltage v in_high 0.7* vddd vdd5v +0.1 v i2 high level input leakage current i in_high 5a i3 low level input voltage (except p_on pin) v in_low 00.8v i4 low level input voltage (at p_on pin) v in_low_pon 00.5v i5 low level input leakage current i in_low -5 a i6 high level output voltage 1 v out_high1 vdd5v -0.4 vdd5v v ioh=-500 a, static driver capability; normal pad mode (see register ppcfg2 and cmc0) i7 low level output voltage 1 v out_low1 0 0.4 v iol=500 a, static driver capability; normal pad mode (see register ppcfg2 and cmc0) i8 high level output voltage 2 v out_high2 vdd5v -0.8 vdd5v v ioh=-4 ma, static driver capability; high power pad mode (see register ppcfg2 and cmc0) i9 low level output voltage 2 v out_low2 0 0.8 v iol=4 ma, static driver capability; high power pad mode (see register ppcfg2 and cmc0) # parameter symbol limit values unit test conditions remarks min. typ. max. data sheet 145 v1.0, 2010-02-19 TDA5235 reference timing spi-bus characteristics j1 clock frequency f clock 2.2 mhz note: a high spi clock rate during data reception can reduce sensitivity j2 clock high time t clk_h 200 ns j3 clock low time t clk_l 200 ns j4 active setup time t setup 200 ns j5 not active setup time t not_setup 200 ns j6 active hold time t hold 200 ns j7 not active hold time t not_hold 200 ns j8 deselect time t deselect 200 ns j9 sdi setup time t sdi_setup 100 ns j10 sdi hold time t sdi_hold 100 ns j11 clock low to sdo valid t clk_sdo 145 ns @ c load = 80 pf high power pad not enabled (normal mode) (see register ppcfg2 and cmc0) j12 clock low to sdo valid t clk_sdo 40 ns @ c load = 10 pf high power pad not enabled (normal mode) (see register ppcfg2 and cmc0) j13 sdo rise time t sdo_r 90 ns @ c load = 80 pf j14 sdo fall time t sdo_f 90 ns @ c load = 80 pf j15 sdo rise time t sdo_r 15 ns @ c load = 10 pf j16 sdo fall time t sdo_f 15 ns @ c load = 10 pf j17 sdo disable time t sdo_disable 25 ns 1) please note that the system bandwidth is smaller than the smallest bandwidth in the signal path. # parameter symbol limit values unit test conditions remarks min. typ. max. TDA5235 reference data sheet 146 v1.0, 2010-02-19 unless explicitly otherwise noted, the following test conditions apply to the given specification values in table 10 and items d7 and d8: * hardware: tda5240 platform testboard v1.0 * single-ended matching for 315.0 mhz / 433.92 mhz / 868.3 mhz / 915.0 mhz * rf input matched to 50 ; insertion loss of input matching network = 1db * receive frequency 315.0 mhz / 433.92 mhz / 868.3 mhz / 915.0 mhz; lo-side lo-injection * reference clock: xtal=21.948717 mhz * if-gain: attenuation set to default value (ifatt = 7) * double down conversion * 1 if-filter: center=10.7mhz; bw=330khz; connected between if_out and ifbuf_in * 2 nd if filter bw: depending on data rate and fsk deviation * received signal at zero offset to if center frequency * rssi trimmed * fsk pre-demodulation filter (pdf) bw: depending on data rate and fsk deviation * no spi-traffic during telegram reception, clk_out disabled * afc and agc are off, unless otherwise noted * specification values are in respect to manchester-coded infineon-reference pattern 1 (7 bits '0', 1 bit ?1', 1 bits '0', 1 bit ?1', 1 bits '0', 1 bit ?1', prbs5 (31 bit), 1 bit 'm') according to figure 18 however a code violation is not used as eom criterion ber sensitivity measurements use receive mode tmmf (sampled with ideal data clock) mer sensitivity measurements use receive mode pof * dre ... data date error of received telegram vs. adjusted data rate * dc ... duty cycle * mer ... message error rate [mer = 1 - (number_of_correctly_received_messages / number_of_transmitted messages)] * far ... false alarm rate [far = number_of_mistakenly_wake_ups / numbe r_of_periods_searching_for_data_on_channel] * mmr ... missed message rate [mmr = number_of_mistakenly_missed_wake_up_patterns / number_of_periods_with_wake_up_pattern_transmitted_and_searching_for_wake_up_pattern] * ber ... bit error rate (using a prbs9 pseudo-random binary sequence) [ber = 1 - (number_of_correctly_received_bits / number_of_transmitted bits)] data sheet 147 v1.0, 2010-02-19 TDA5235 reference table 10 mer characteristics (receive mode = pof) # parameter symbol limit values unit test conditions remarks min. typ. max. characteristics of digital data filter and data clock recovery acceptance criterion is: mer <= 10%. for additional test conditions see right before this table. double down conversion mode k1 data rate error of received telegram sensitivity loss < 1db db -10 10 % at dc = 50% k2 duty cycle error of manchester coding of received telegram k2.1 sensitivity loss < 1db tolmanch_defb 45 55 % according to definition b in chapter 2.7.2 ; including dre of -10% to +10%; data rate < 50 kbit/s k2.2 sensitivity loss < 3.5db tolmanch_defc 35 55 % according to definition c in chapter 2.7.2 including dre of -10% to +10% data rate < 10 kbit/s k2.3 sensitivity loss < 1.5db tolmanch_defb 45 55 % according to definition b in chapter 2.7.2 ; including dre of -10% to +10%; data rate >= 50 kbit/s k2.4 sensitivity loss < 4db tolmanch_defc 35 55 % according to definition c in chapter 2.7.2 including dre of -10% to +10% data rate >= 10 kbit/s note: if bpf_bw / bitrate < 12, the selected data rate in the configuration tool needs to be set 5% higher. TDA5235 reference data sheet 148 v1.0, 2010-02-19 sensitivity of receiver acceptance criterion is: mer <= 10%. for additional test conditions see right before this table. double down conversion mode l1 sensitivity limit in ask (ook) mode; manchester coding at dc = 50% and dre = 0%. t amb = 25 c, peak power level (see chapter 2.7.3 ) l1.1 data rate 0.5 kbit/s sask1 -120 -117 dbm peak m = 100% 2 nd if bw = 50 khz; ifatt = 0, cdr = normal; data slicer bit mode; 868/915mhz: <=1db loss l1.2 data rate 2 kbit/s sask2 -116 -113 dbm peak m = 100% 2 nd if bw = 50 khz; ifatt = 0, cdr = normal; data slicer bit mode l1.3 data rate 10 kbit/s sask3 -111 -108 dbm peak m = 100% 2 nd if bw = 50 khz; ifatt = 0, cdr = normal; data slicer bit mode l1.4 data rate 16 kbit/s sask4 -109 -106 dbm peak m = 100% 2 nd if bw = 80 khz; ifatt = 0, cdr = normal; data slicer bit mode; 868/915mhz: <=1db loss l1.5 data rate 0.5 kbit/s sask5 -115 -112 dbm peak m = 100% 2 nd if bw = 300 khz; ifatt = 7, cdr = fast; data slicer bit mode; note: 3db sensitivity loss @ f offset = +/-100 khz l1.6 data rate 2 kbit/s sask6 -112 -109 dbm peak m = 100% 2 nd if bw = 300 khz; ifatt = 7, cdr = fast; data slicer bit mode; 868/915mhz: <=1db loss; note: 3db sensitivity loss @ f offset = +/-100 khz l1.7 data rate 10 kbit/s sask7 -106 -103 dbm peak m = 100% 2 nd if bw = 300 khz; ifatt = 7, cdr = fast; data slicer bit mode; note: 3db sensitivity loss @ f offset = +/-100 khz # parameter symbol limit values unit test conditions remarks min. typ. max. data sheet 149 v1.0, 2010-02-19 TDA5235 reference l1.8 data rate 16 kbit/s sask8 -104 -101 dbm peak m = 100% 2 nd if bw = 300 khz; ifatt = 7, cdr = fast; data slicer bit mode; note: 3db sensitivity loss @ f offset = +/-100 khz l2 sensitivity limit in fsk mode; manchester coding at dc = 50% and dre = 0%. t amb = 25 c l2.1 data rate 2 kbit/s; f = 10 khz sfsk1 -118 -115 dbm 2 nd if bw = 50 khz; pdf = 33 khz, afc off; ifatt = 0, cdr = normal; data slicer bit mode l2.2 data rate 10 kbit/s; f = 14 khz sfsk2 -113 -110 dbm 2 nd if bw = 50 khz; pdf = 65 khz, afc off; ifatt = 0, cdr = normal; data slicer bit mode l2.3 data rate 10 kbit/s; f = 50 khz sfsk3 -112 -109 dbm 2 nd if bw = 125 khz; pdf = 132 khz, afc off; ifatt = 0, cdr = normal; data slicer bit mode; 868/915mhz: <=1db loss l2.4 data rate 50 kbit/s; f = 50 khz sfsk4 -106 -103 dbm 2 nd if bw = 300 khz; pdf = 239 khz, afc off; ifatt = 0, cdr = normal; data slicer bit mode l2.5 data rate 2 kbit/s; f = 10 khz sfsk5 -108 -105 dbm 2 nd if bw = 300 khz; pdf = 282 khz; ifatt = 7, cdr = fast; data slicer bit mode; 868/915mhz: <=1db loss; note: 3db sensitivity loss @ f offset =+/-90khz @ afc on l2.6 data rate 10 kbit/s; f = 14 khz sfsk6 -107 -104 dbm 2 nd if bw = 300 khz; pdf = 282 khz; ifatt = 7, cdr = fast; data slicer bit mode; note: 3db sensitivity loss @ f offset =+/-90khz @ afc on l2.7 data rate 10 kbit/s; f = 50 khz sfsk7 -109 -106 dbm 2 nd if bw = 300 khz; pdf = 282 khz; ifatt = 7, cdr = fast; data slicer bit mode; note: 3db sensitivity loss @ f offset =+/-90khz @ afc on # parameter symbol limit values unit test conditions remarks min. typ. max. TDA5235 reference data sheet 150 v1.0, 2010-02-19 dynamic range of receiver acceptance criteria are: mer <= 1e-3, far < 1e-5, mmr < 1e-4 (criterion: 8 equal bits), manchester coding. for additional test conditions see right before this table. double down conversion mode m1 dynamic range in ask (ook) mode, agc on at dc = 50% and dre = 0%. t amb = 25 c, peak power level (see chapter 2.7.3 ) m1.1 data rate 2 kbit/s dr2,ook -10 -109 dbm peak m = 100% 2 nd if bw = 50 khz; ifatt = 0, cdr = normal; data slicer bit mode m1.2 data rate 10 kbit/s dr10,ook -10 -105 dbm peak m = 100% 2 nd if bw = 50 khz; ifatt = 0, cdr = normal; data slicer bit mode m1.3 data rate 2 kbit/s dr2,ask50 -45 -103 dbm peak m = 50% 2 nd if bw = 50 khz; ifatt = 0, cdr = normal; data slicer bit mode m1.4 data rate 10 kbit/s dr10,ask50 -60 -99 dbm peak m = 50% 2 nd if bw = 50 khz; ifatt = 0, cdr = normal; data slicer bit mode m2 dynamic range in fsk mode, agc on data rate 10 kbit/s & f = 50 khz at dc = 50% and dre = 0%. t amb = 25 c m2.1 0% am modulation dr10,am0 -10 -106 dbm 2 nd if bw = 125 khz pdf = 132 khz; ifatt = 0, cdr = normal; data slicer bit mode m2.2 90% am modulation, 100 hz dr10,am90 -10 -90 dbm 2 nd if bw = 125 khz pdf = 132 khz; ifatt = 0, cdr = normal; data slicer bit mode # parameter symbol limit values unit test conditions remarks min. typ. max. data sheet 151 v1.0, 2010-02-19 TDA5235 reference table 11 typical achievable sensitivity bandwidth [khz] ceramic filter bw = 330 khz table is valid for ddc (double down conversion) and sdc (single down conversion) valid for afc=off; for fsk & afc=on the bw can be increased by 2*afclimit, where afclimit < 43 khz bpf/pdf filter [hz] modulation fsk deviation [+/- hz] sensitivity loss data rate [bit/s], manchester 0.5 k 1 k 5 10 k 20 k 50 k bpf = 300 k pdf = 282 k ask - 3 db 230 230 230 230 230 - 6 db 280 280 280 280 280 - fsk 0.5 k 3 db 160 150 - - - - 6 db 230 220 - - - - 1 k 3 db 140 160 - - - - 6 db 220 230 - - - - 5 k 3 db 120 130 150 140 - - 6 db 200 210 220 220 - - 10 k 3 db 120 120 140 140 150 - 6 db 180 190 210 210 210 - 15 k 3 db - - 130 140 150 - 6 db - - 200 200 210 - 20 k 3 db 110 - 130 130 140 - 6 db 160 - 190 190 190 - 40 k 3 db - - - 120 - - 6 db - - - 160 - - 50 k 3 db 110 110 110 110 100 100 6 db 140 140 140 140 140 140 TDA5235 reference data sheet 152 v1.0, 2010-02-19 bpf = 200 k pdf = 239 k ask - 3 db 180 180 180 180 180 - 6 db 220 220 220 220 220 - fsk 0.5 k 3 db 140 140 - - - - 6 db 190 190 - - - - 1 k 3 db 130 130 - - - - 6 db 180 190 - - - - 5 k 3 db 100 120 130 130 - - 6 db 160 170 180 180 - - 10 k 3 db 100 100 120 120 140 - 6 db 140 150 170 170 170 - 15 k 3 db - - 110 110 120 - 6 db - - 150 150 160 - 20 k 3 db 90 - 100 100 110 - 6 db 130 - 140 150 150 - 40 k 3 db - - - 90 - - 6 db - - - 120 - - 50 k 3 db ------ 6 db ------ table 11 typical achievable sensitivity bandwidth [khz] ceramic filter bw = 330 khz table is valid for ddc (double down conversion) and sdc (single down conversion) valid for afc=off; for fsk & afc=on the bw can be increased by 2*afclimit, where afclimit < 43 khz bpf/pdf filter [hz] modulation fsk deviation [+/- hz] sensitivity loss data rate [bit/s], manchester 0.5 k 1 k 5 10 k 20 k 50 k data sheet 153 v1.0, 2010-02-19 TDA5235 reference bpf = 125 k pdf = 132 k ask - 3 db 120 120 120 120 120 - 6 db 150 150 150 150 150 - fsk 0.5 k 3 db 100 100 - - - - 6 db 120 120 - - - - 1 k 3 db 90 100 - - - - 6 db 120 120 - - - - 5 k 3 db 70 80 80 90 - - 6 db 100 110 110 110 - - 10 k 3 db 70 70 80 80 80 - 6 db 90 100 100 100 100 - 15 k 3 db - - 70 80 80 - 6 db - - 90 90 100 - 20 k 3 db 60 - 70 70 70 - 6 db 80 - 90 90 90 - 40 k 3 db ------ 6 db ------ 50 k 3 db ------ 6 db ------ table 11 typical achievable sensitivity bandwidth [khz] ceramic filter bw = 330 khz table is valid for ddc (double down conversion) and sdc (single down conversion) valid for afc=off; for fsk & afc=on the bw can be increased by 2*afclimit, where afclimit < 43 khz bpf/pdf filter [hz] modulation fsk deviation [+/- hz] sensitivity loss data rate [bit/s], manchester 0.5 k 1 k 5 10 k 20 k 50 k TDA5235 reference data sheet 154 v1.0, 2010-02-19 4.2 test circuit - evaluation board v1.0 figure 94 test circuit schematic data sheet 155 v1.0, 2010-02-19 TDA5235 reference 4.3 test board layout, evaluation board v1.0 figure 95 test board layout, top view figure 96 test board layout, bottom view TDA5235 reference data sheet 156 v1.0, 2010-02-19 figure 97 test board layout, component view data sheet 157 v1.0, 2010-02-19 TDA5235 reference 4.4 bill of materials pos part value package device / type tolerance manufacturer remark/options (rf+supply variant) 1 ic1 TDA5235 pg-tssop-28 infineon 2 c1 3.9 pf 0603 c0g +/- 0.1 pf crystal oscillator load 3 c2 3.9 pf 0603 c0g +/- 0.1 pf crystal oscillator load 4 c3 100 nf 0603 x7r +/- 10 % 5 c4 100 nf 0603 x7r +/- 10 % 6 c5 100 nf / ( 1 f ) 0603 x7r / x5r +/- 10 % 3.3v / ( 5 v environment) 7 c6 100 nf 0603 x7r +/- 10 % 8 c7 1 pf 0603 c0g +/- 0.1 pf matching for 315mhz 0.5 pf 0603 c0g +/- 0.1 pf matching for 434mhz open 0603 c0g matching for 868mhz 1 pf 0603 c0g +/- 0.1 pf matching for 915mhz 9 c8 open 0603 c0g matching for 315mhz open 0603 c0g matching for 434mhz 2.7 pf 0603 c0g +/- 0.1 pf matching for 868mhz 5.1 pf 0603 c0g +/- 0.1 pf matching for 915mhz 10 c9 1 f smc-a tantal +/- 10% polarized capacitor 11 c10 100 nf 0603 x7r +/- 10% 12 c11 10 nf 0603 x7r +/- 10% 13 l1 68 nh 0603 +/- 2% matching for 315mhz 39 nh 0603 +/- 2% matching for 434mhz 22 nh 0603 +/- 2% matching for 868mhz 15 nh 0603 +/- 2% matching for 915mhz 14 r1 10 ohm / (open) 0603 +/- 5% 3.3 v / ( 5 v environment) 15 r2 4.7 ohm / (open) 0603 +/- 5% 3.3 v / ( 5 v environment) 16 r3 4.7 ohm / (22 ohm) 0603 +/- 5% 3.3 v / ( 5 v environment) 17 r4 0 ohm 0603 18 if1 sfecf10 m7ea00 murata bw = 330 khz 19 q1 21.948717 mhz nx5032sd c0=1.7 pf c1=7 ff cl=12 pf ndk (frischer electronic), exs00a- cs01580 smd crystal TDA5235 reference data sheet 158 v1.0, 2010-02-19 interface / optional 20 ic2 at24c32 c-sh-b or at24c512 soic8 eeprom for board detection 21 c12 open 0603 x7r +/- 10% rssi measurement low pass 22 c13 100 nf 0603 x7r +/- 10% 23 c14 1 f smc-a tantal +/- 10% polarized capacitor 24 c15 10 nf 0603 x7r +/- 10% filter network on supply line 25 c16 10 nf 0603 x7r +/- 10% filter network on supply line 26 l2 0 ohm 0603 no filter network on supply line 27 r5 open 0603 rssi measurement low pass 28 r6 1 kohm 0603 29 r7 0 ohm 0603 write protection for eeprom 30 d1 led ls m676- p251-1 status indication led 31 if2 open murata 2nd if filter is optional 32 x1 sma socket rf input 33 x2 3 pins board supply 34 x3 2 pins chip supply current (jumper closed) 35 x4 50 pins sib-qts-025- 01-x-d-ra samtec connector to pc/c/interface 36 x5 2 pins rssi measuring point 37 x6 12 pins interface line measuring point 38 x7 4 pins gnd 39 x8 4 pins gnd 40 jum- per 1 2 pins jumper for x3 41 jum- per 2 2 pins jumper for x2 - supply by interface board material 1.5mm fr4 with 35m copper on both sides pos part value package device / type tolerance manufacturer remark/options (rf+supply variant) data sheet 159 v1.0, 2010-02-19 TDA5235 package outlines 5 package outlines figure 98 pg-tssop-28 package outline (green package) table 12 order information type ordering code package TDA5235 sp000507674 pg-tssop-28 does not include dambar protrusion does not include plastic or metal protrusion of 0.15 max. per side 1 28 index marking 1) ?.1 9.7 a 14 15 0.1 m 28x ac 0.65 0.22 2) -0.03 +0.08 0.1 ?.05 c 0.1 +0.05 -0.2 1.2 max. 1 -0.035 b 0.125 +0.075 ?.1 4.4 1) ...8? +0.15 0.6 0? 0.2 6.4 -0.1 2 8x b 1) 2) you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products dimensions in mm smd = surface mounted device TDA5235 list of tables page data sheet 160 v1.0, 2010-02-19 table 1 pin definition and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2 agc settings 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 3 agc settings 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 4 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 5 spi bus timing parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 6 power level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 7 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 8 supply operating range and ambient temperature . . . . . . . . . . . . . 132 table 9 ac/dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 10 mer characteristics (receive mode = pof) . . . . . . . . . . . . . . . . . . 147 table 11 typical achievable sensitivity bandwidth [khz] . . . . . . . . . . . . . . . . . 151 table 12 order information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 TDA5235 list of figures page data sheet 161 v1.0, 2010-02-19 figure 1 pin-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2 TDA5235 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 3 block diagram rf section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 4 single down conversion (sdc, no external filters required) . . . . . . . . 20 figure 5 double down conversion (ddc) with one external filter . . . . . . . . . . . 21 figure 6 double down conversion (ddc) with two external filters . . . . . . . . . . 21 figure 7 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8 external clock generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 9 synthesizer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 10 functional block diagram ask/fsk demodulator . . . . . . . . . . . . . . . 27 figure 11 afc loop filter (i-pi filtering and mapping) . . . . . . . . . . . . . . . . . . . . 29 figure 12 analog rssi output curve with agc action on (blue) vs. off (black) 30 figure 13 peak detector unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 14 peak detector behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 15 functional block diagram digital baseband receiver. . . . . . . . . . . . . 38 figure 16 signal detector threshold level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 17 coding schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 18 manchester symbols including code violations . . . . . . . . . . . . . . . . . 42 figure 19 clock recovery (adpll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 20 runin generation principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 21 definition of tolerance windows for the cdr . . . . . . . . . . . . . . . . . . . 46 figure 22 data rate acceptance limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 23 wake-up generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 24 rssi blocking thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 25 wake-up data criteria search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 26 frame synchronization unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 27 16-bit tsi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 28 8-bit parallel tsi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 29 8-bit extended tsi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 30 8-bit gap tsi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 31 clock recovery gap resynchronization mode tsigrsyn = 1 . . . . . 60 figure 32 clock recovery gap resynchronization mode tsigrsyn = 0 . . . . . 61 figure 33 tsigap tsib timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 34 tvwin and tsigap dependency example . . . . . . . . . . . . . . . . . . . . . 62 figure 35 4-byte message id scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 36 2-byte message id scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 37 mid scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 38 structure of payload frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 39 data latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 40 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 41 3.3 volts and 5 volts applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 42 supply current ramp up/down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 TDA5235 data sheet 162 v1.0, 2010-02-19 figure 43 reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 44 logical and electrical system interfaces of the TDA5235 . . . . . . . . . . 75 figure 45 receive modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 46 data interface for the packet oriented fifo mode . . . . . . . . . . . . . . . 77 figure 47 data interface for the packet oriented transparent payload mode . . 77 figure 48 timing of the packet oriented transparent payload mode . . . . . . . . . 78 figure 49 data interface for the transparent mode - chip data and strobe . . . . 78 figure 50 timing of the transparent mode - chip data and strobe . . . . . . . . . . 79 figure 51 data interface for the transparent modes tmmf / tmrds . . . . . . . . 79 figure 52 external data processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 53 receive fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 54 fifo lock behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 55 spi data fifo read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 56 interrupt generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 57 interrupt generation waveform (example for configuration a+b). . . . 87 figure 58 isx readout set clear collision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 59 read register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 60 burst read registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 61 write register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 62 burst write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 63 spi checksum generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 64 read fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 65 serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 66 serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 67 chip serial number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 68 global state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 69 run mode slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 70 hold state behavior (initpllhold disabled) . . . . . . . . . . . . . . . . . 99 figure 71 hold state behavior (initpllhold enabled) . . . . . . . . . . . . . . . . . 99 figure 72 spm - tx-rx interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 73 wake-up search with configuration a . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 74 wake-up search with configuration b . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 75 totim behavior without presence of interferer . . . . . . . . . . . . . . . . 105 figure 76 totim behavior in presence of interferer . . . . . . . . . . . . . . . . . . . . . 106 figure 77 run mode self polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 78 parallel wake-up search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 79 polling timer unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 80 constant on-off time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 81 coo polling in wu on rssi mode . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 82 ultrafast fall back to sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 83 uffb activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 84 fast fall back to sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 85 mixed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 data sheet 163 v1.0, 2010-02-19 TDA5235 figure 86 permanent wake-up search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 87 active idle period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 88 definition a: level-based definition . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 89 definition b: chip-based definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 90 definition c: edge delay definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 91 sfr symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 92 sfr address paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 93 typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 94 test circuit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 95 test board layout, top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 96 test board layout, bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 97 test board layout, component view . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 98 pg-tssop-28 package outline (green package). . . . . . . . . . . . . . . 159 TDA5235 data sheet 164 v1.0, 2010-02-19 data sheet 165 v1.0, 2010-02-19 TDA5235 appendix - registers chapter TDA5235 appendix register overview data sheet 166 v1.0, 2010-02-19 appendix - registers chapter register overview table 1 register overview register short name register long name offset address page number appendix - registers chapter , register description a_mid0 message id register 0 000 h 179 a_mid1 message id register 1 001 h 179 a_mid2 message id register 2 002 h 179 a_mid3 message id register 3 003 h 180 a_mid4 message id register 4 004 h 180 a_mid5 message id register 5 005 h 180 a_mid6 message id register 6 006 h 181 a_mid7 message id register 7 007 h 181 a_mid8 message id register 8 008 h 182 a_mid9 message id register 9 009 h 182 a_mid10 message id register 10 00a h 182 a_mid11 message id register 11 00b h 183 a_mid12 message id register 12 00c h 183 a_mid13 message id register 13 00d h 183 a_mid14 message id register 14 00e h 184 a_mid15 message id register 15 00f h 184 a_mid16 message id register 16 010 h 184 a_mid17 message id register 17 011 h 185 a_mid18 message id register 18 012 h 185 a_mid19 message id register 19 013 h 186 a_midc0 message id control register 0 014 h 186 a_midc1 message id control register 1 015 h 186 a_if1 if1 register 016 h 187 a_wuc wake-up control register 017 h 188 a_wupat0 wake-up pattern register 0 018 h 189 a_wupat1 wake-up pattern register 1 019 h 190 a_wubcnt wake-up bit or chip count register 01a h 190 a_wurssith1 rssi wake-up threshold for channel 1 register 01b h 191 a_wurssibl1 rssi wake-up blocking level low channel 1 register 01c h 191 a_wurssibh1 rssi wake-up blocking level high channel 1 register 01d h 192 a_sigdetsat signal detector saturation threshold register 024 h 192 TDA5235 appendix register overview data sheet 167 v1.0, 2010-02-19 a_wulot wake-up on level observation time register 025 h 193 a_sysrcto synchronization search time-out register 026 h 193 a_totim_sync sync timeout timer register 027 h 194 a_totim_tsi tsi timeout timer register 028 h 194 a_totim_eom eom timeout timer register 029 h 195 a_afclimit afc limit configuration register 02a h 195 a_afcagcd afc/agc freeze delay register 02b h 196 a_afcsfcfg afc start/freeze configuration register 02c h 196 a_afck1cfg0 afc integrator 1 gain register 0 02d h 197 a_afck1cfg1 afc integrator 1 gain register 1 02e h 198 a_afck2cfg0 afc integrator 2 gain register 0 02f h 198 a_afck2cfg1 afc integrator 2 gain register 1 030 h 198 a_pmfudsf peak memory filter up-down factor register 031 h 199 a_agcsfcfg agc start/freeze configuration register 032 h 200 a_agccfg0 agc configuration register 0 033 h 201 a_agccfg1 agc configuration register 1 034 h 202 a_agcthr agc threshold register 035 h 202 a_digrxc digital receiver configuration register 036 h 202 a_pkbitpos rssi peak detector bit position register 037 h 204 a_isupfcsel image supression fc selection register 038 h 204 a_pdecf pre decimation factor register 039 h 205 a_pdecscfsk pre decimation scaling register fsk mode 03a h 205 a_pdecscask pre decimation scaling register ask mode 03b h 205 a_mfc matched filter control register 03c h 206 a_src sampe rate converter nco tune 03d h 206 a_extslc externel data slicer configuration 03e h 207 a_sigdet0 signal detector threshold level register - run mode 03f h 207 a_sigdet1 signal detector threshold level register - wakeup 040 h 208 a_sigdetlo signal detector threshold low level register 041 h 208 a_sigdetsel signal detector range selection register 042 h 209 a_sigdetcfg signal detector configuration register 043 h 210 a_ndthres fsk noise detector threshold register 044 h 210 a_ndconfig fsk noise detector configuration register 045 h 211 a_cdrp clock and data recovery p configuration register 046 h 211 a_cdri clock and data recovery configuration register 047 h 212 table 1 register overview (cont?d) register short name register long name offset address page number TDA5235 appendix register overview data sheet 168 v1.0, 2010-02-19 a_cdrri clock and data recovery runin configuration register 048 h 214 a_cdrtolc cdr dc chip tolerance register 049 h 214 a_cdrtolb cdr dc bit tolerance register 04a h 215 a_tvwin timing violation window register 04b h 216 a_slccfg slicer configuration register 04c h 216 a_tsimode tsi detection mode register 04d h 217 a_tsilena tsi length register a 04e h 217 a_tsilenb tsi length register b 04f h 218 a_tsigap tsi gap length register 050 h 218 a_tsipta0 tsi pattern data reference a register 0 051 h 219 a_tsipta1 tsi pattern data reference a register 1 052 h 219 a_tsiptb0 tsi pattern data reference b register 0 053 h 220 a_tsiptb1 tsi pattern data reference b register 1 054 h 220 a_eomc end of message control register 055 h 220 a_eomdlen eom data length limit register 056 h 221 a_eomdlenp eom data length limit parallel mode register 057 h 222 a_chcfg channel configuration register 058 h 222 a_pllintc1 pll mmd integer value register channel 1 059 h 223 a_pllfrac0c1 pll fractional division ratio register 0 channel 1 05a h 224 a_pllfrac1c1 pll fractional division ratio register 1 channel 1 05b h 224 a_pllfrac2c1 pll fractional division ratio register 2 channel 1 05c h 225 sfrpage special function register page register 080 h 225 ppcfg0 pp0 and pp1 configuration register 081 h 226 ppcfg1 pp2 and pp3 configuration register 082 h 227 ppcfg2 ppx port configuration register 083 h 228 rxruncfg0 rx run configuration register 0 084 h 229 rxruncfg1 rx run configuration register 1 085 h 230 clkout0 clock divider register 0 086 h 231 clkout1 clock divider register 1 087 h 231 clkout2 clock divider register 2 088 h 232 rfc rf control register 089 h 232 bpfcalcfg0 bpf calibration configuration register 0 08a h 233 bpfcalcfg1 bpf calibration configuration register 1 08b h 234 xtalcal0 xtal coarse calibration register 08c h 234 xtalcal1 xtal fine calibration register 08d h 235 rssimonc rssi monitor configuration register 08e h 235 adcinsel adc input selection register 08f h 236 rssioffs rssi offset register 090 h 236 table 1 register overview (cont?d) register short name register long name offset address page number TDA5235 appendix register overview data sheet 169 v1.0, 2010-02-19 rssislope rssi slope register 091 h 237 cdrdrthrp cdr data rate acceptance positive threshold register 092 h 237 cdrdrthrn cdr data rate acceptance negative threshold register 093 h 238 im0 interrupt mask register 0 094 h 238 spmap self polling mode active periods register 096 h 239 spmip self polling mode idle periods register 097 h 240 spmc self polling mode control register 098 h 240 spmrt self polling mode reference timer register 099 h 241 spmofft0 self polling mode off time register 0 09a h 241 spmofft1 self polling mode off time register 1 09b h 242 spmonta0 self polling mode on time config a register 0 09c h 242 spmonta1 self polling mode on time config a register 1 09d h 243 spmontb0 self polling mode on time config b register 0 09e h 243 spmontb1 self polling mode on time config b register 1 09f h 244 extpcmd external processing command register 0a4 h 244 cmc1 chip mode control register 1 0a5 h 245 cmc0 chip mode control register 0 0a6 h 246 rssipwu wakeup peak detector readout register 0a7 h 247 is0 interrupt status register 0 0a8 h 248 rfpllacc rf pll actual channel and configuration register 0aa h 249 rssiprx rssi peak detector readout register 0ab h 250 rssippl rssi payload peak detector readout register 0ac h 250 pldlen payload data length register 0ad h 251 adcresh adc result high byte register 0ae h 251 adcresl adc result low byte register 0af h 252 vacres vco autocalibration result readout register 0b0 h 252 afcoffset afc offset read register 0b1 h 252 agcgainr agc gain readout register 0b2 h 253 spiat spi address tracer register 0b3 h 253 spidt spi data tracer register 0b4 h 254 spichksum spi checksum register 0b5 h 254 sn0 serial number register 0 0b6 h 255 sn1 serial number register 1 0b7 h 255 sn2 serial number register 2 0b8 h 255 sn3 serial number register 3 0b9 h 256 rssirx rssi readout register 0ba h 256 table 1 register overview (cont?d) register short name register long name offset address page number TDA5235 appendix register overview data sheet 170 v1.0, 2010-02-19 rssipmf rssi peak memory filter readout register 0bb h 256 spwr signal power readout register 0bc h 257 npwr noise power readout register 0bd h 257 b_mid0 message id register 0 100 h b_mid1 message id register 1 101 h b_mid2 message id register 2 102 h b_mid3 message id register 3 103 h b_mid4 message id register 4 104 h b_mid5 message id register 5 105 h b_mid6 message id register 6 106 h b_mid7 message id register 7 107 h b_mid8 message id register 8 108 h b_mid9 message id register 9 109 h b_mid10 message id register 10 10a h b_mid11 message id register 11 10b h b_mid12 message id register 12 10c h b_mid13 message id register 13 10d h b_mid14 message id register 14 10e h b_mid15 message id register 15 10f h b_mid16 message id register 16 110 h b_mid17 message id register 17 111 h b_mid18 message id register 18 112 h b_mid19 message id register 19 113 h b_midc0 message id control register 0 114 h b_midc1 message id control register 1 115 h b_if1 if1 register 116 h b_wuc wake-up control register 117 h b_wupat0 wake-up pattern register 0 118 h b_wupat1 wake-up pattern register 1 119 h b_wubcnt wake-up bit or chip count register 11a h b_wurssith1 rssi wake-up threshold for channel 1 register 11b h b_wurssibl1 rssi wake-up blocking level low channel 1 register 11c h b_wurssibh1 rssi wake-up blocking level high channel 1 register 11d h b_sigdetsat signal detector saturation threshold register 124 h b_wulot wake-up on level observation time register 125 h b_sysrcto synchronization search time-out register 126 h b_totim_sync sync timeout timer register 127 h table 1 register overview (cont?d) register short name register long name offset address page number TDA5235 appendix register overview data sheet 171 v1.0, 2010-02-19 b_totim_tsi tsi timeout timer register 128 h b_totim_eom eom timeout timer register 129 h b_afclimit afc limit configuration register 12a h b_afcagcd afc/agc freeze delay register 12b h b_afcsfcfg afc start/freeze configuration register 12c h b_afck1cfg0 afc integrator 1 gain register 0 12d h b_afck1cfg1 afc integrator 1 gain register 1 12e h b_afck2cfg0 afc integrator 2 gain register 0 12f h b_afck2cfg1 afc integrator 2 gain register 1 130 h b_pmfudsf peak memory filter up-down factor register 131 h b_agcsfcfg agc start/freeze configuration register 132 h b_agccfg0 agc configuration register 0 133 h b_agccfg1 agc configuration register 1 134 h b_agcthr agc threshold register 135 h b_digrxc digital receiver configuration register 136 h b_pkbitpos rssi peak detector bit position register 137 h b_isupfcsel image supression fc selection register 138 h b_pdecf pre decimation factor register 139 h b_pdecscfsk pre decimation scaling register fsk mode 13a h b_pdecscask pre decimation scaling register ask mode 13b h b_mfc matched filter control register 13c h b_src sampe rate converter nco tune 13d h b_extslc externel data slicer configuration 13e h b_sigdet0 signal detector threshold level register - run mode 13f h b_sigdet1 signal detector threshold level register - wakeup 140 h b_sigdetlo signal detector threshold low level register 141 h b_sigdetsel signal detector range selection register 142 h b_sigdetcfg signal detector configuration register 143 h b_ndthres fsk noise detector threshold register 144 h b_ndconfig fsk noise detector configuration register 145 h b_cdrp clock and data recovery p configuration register 146 h b_cdri clock and data recovery configuration register 147 h b_cdrri clock and data recovery runin configuration register 148 h b_cdrtolc cdr dc chip tolerance register 149 h b_cdrtolb cdr dc bit tolerance register 14a h table 1 register overview (cont?d) register short name register long name offset address page number TDA5235 appendix register overview data sheet 172 v1.0, 2010-02-19 b_tvwin timing violation window register 14b h b_slccfg slicer configuration register 14c h b_tsimode tsi detection mode register 14d h b_tsilena tsi length register a 14e h b_tsilenb tsi length register b 14f h b_tsigap tsi gap length register 150 h b_tsipta0 tsi pattern data reference a register 0 151 h b_tsipta1 tsi pattern data reference a register 1 152 h b_tsiptb0 tsi pattern data reference b register 0 153 h b_tsiptb1 tsi pattern data reference b register 1 154 h b_eomc end of message control register 155 h b_eomdlen eom data length limit register 156 h b_eomdlenp eom data length limit parallel mode register 157 h b_chcfg channel configuration register 158 h b_pllintc1 pll mmd integer value register channel 1 159 h b_pllfrac0c1 pll fractional division ratio register 0 channel 1 15a h b_pllfrac1c1 pll fractional division ratio register 1 channel 1 15b h b_pllfrac2c1 pll fractional division ratio register 2 channel 1 15c h table 2 register overview and reset value register short name register long name offset address reset value appendix - registers chapter , register description a_mid0 message id register 0 000 h 00 h a_mid1 message id register 1 001 h 00 h a_mid2 message id register 2 002 h 00 h a_mid3 message id register 3 003 h 00 h a_mid4 message id register 4 004 h 00 h a_mid5 message id register 5 005 h 00 h a_mid6 message id register 6 006 h 00 h a_mid7 message id register 7 007 h 00 h a_mid8 message id register 8 008 h 00 h a_mid9 message id register 9 009 h 00 h a_mid10 message id register 10 00a h 00 h a_mid11 message id register 11 00b h 00 h a_mid12 message id register 12 00c h 00 h a_mid13 message id register 13 00d h 00 h a_mid14 message id register 14 00e h 00 h a_mid15 message id register 15 00f h 00 h table 1 register overview (cont?d) register short name register long name offset address page number TDA5235 appendix register overview data sheet 173 v1.0, 2010-02-19 a_mid16 message id register 16 010 h 00 h a_mid17 message id register 17 011 h 00 h a_mid18 message id register 18 012 h 00 h a_mid19 message id register 19 013 h 00 h a_midc0 message id control register 0 014 h 00 h a_midc1 message id control register 1 015 h 00 h a_if1 if1 register 016 h 20 h a_wuc wake-up control register 017 h 04 h a_wupat0 wake-up pattern register 0 018 h 00 h a_wupat1 wake-up pattern register 1 019 h 00 h a_wubcnt wake-up bit or chip count register 01a h 00 h a_wurssith1 rssi wake-up threshold for channel 1 register 01b h 00 h a_wurssibl1 rssi wake-up blocking level low channel 1 register 01c h ff h a_wurssibh1 rssi wake-up blocking level high channel 1 register 01d h 00 h a_sigdetsat signal detector saturation threshold register 024 h 10 h a_wulot wake-up on level observation time register 025 h 00 h a_sysrcto synchronization search time-out register 026 h 87 h a_totim_sync sync timeout timer register 027 h ff h a_totim_tsi tsi timeout timer register 028 h 00 h a_totim_eom eom timeout timer register 029 h 00 h a_afclimit afc limit configuration register 02a h 02 h a_afcagcd afc/agc freeze delay register 02b h 00 h a_afcsfcfg afc start/freeze configuration register 02c h 00 h a_afck1cfg0 afc integrator 1 gain register 0 02d h 00 h a_afck1cfg1 afc integrator 1 gain register 1 02e h 00 h a_afck2cfg0 afc integrator 2 gain register 0 02f h 00 h a_afck2cfg1 afc integrator 2 gain register 1 030 h 00 h a_pmfudsf peak memory filter up-down factor register 031 h 42 h a_agcsfcfg agc start/freeze configuration register 032 h 00 h a_agccfg0 agc configuration register 0 033 h 2b h a_agccfg1 agc configuration register 1 034 h 03 h a_agcthr agc threshold register 035 h 08 h a_digrxc digital receiver configuration register 036 h 40 h a_pkbitpos rssi peak detector bit position register 037 h 00 h a_isupfcsel image supression fc selection register 038 h 07 h a_pdecf pre decimation factor register 039 h 00 h a_pdecscfsk pre decimation scaling register fsk mode 03a h 00 h table 2 register overview and reset value (cont?d) register short name re gister long name offset address reset value TDA5235 appendix register overview data sheet 174 v1.0, 2010-02-19 a_pdecscask pre decimation scaling register ask mode 03b h 20 h a_mfc matched filter control register 03c h 07 h a_src sampe rate converter nco tune 03d h 00 h a_extslc externel data slicer configuration 03e h 02 h a_sigdet0 signal detector threshold level register - run mode 03f h 00 h a_sigdet1 signal detector threshold level register - wakeup 040 h 00 h a_sigdetlo signal detector threshold low level register 041 h 00 h a_sigdetsel signal detector range selection register 042 h 7f h a_sigdetcfg signal detector configuration register 043 h 00 h a_ndthres fsk noise detector threshold register 044 h 00 h a_ndconfig fsk noise detector configuration register 045 h 07 h a_cdrp clock and data recovery p configuration register 046 h e6 h a_cdri clock and data recovery configuration register 047 h 65 h a_cdrri clock and data recovery runin configuration register 048 h 01 h a_cdrtolc cdr dc chip tolerance register 049 h 0c h a_cdrtolb cdr dc bit tolerance register 04a h 1e h a_tvwin timing violation window register 04b h 28 h a_slccfg slicer configuration register 04c h 90 h a_tsimode tsi detection mode register 04d h 80 h a_tsilena tsi length register a 04e h 00 h a_tsilenb tsi length register b 04f h 00 h a_tsigap tsi gap length register 050 h 00 h a_tsipta0 tsi pattern data reference a register 0 051 h 00 h a_tsipta1 tsi pattern data reference a register 1 052 h 00 h a_tsiptb0 tsi pattern data reference b register 0 053 h 00 h a_tsiptb1 tsi pattern data reference b register 1 054 h 00 h a_eomc end of message control register 055 h 05 h a_eomdlen eom data length limit register 056 h 00 h a_eomdlenp eom data length limit parallel mode register 057 h 00 h a_chcfg channel configuration register 058 h 04 h a_pllintc1 pll mmd integer value register channel 1 059 h 93 h a_pllfrac0c1 pll fractional division ratio register 0 channel 1 05a h f3 h a_pllfrac1c1 pll fractional division ratio register 1 channel 1 05b h 07 h a_pllfrac2c1 pll fractional division ratio register 2 channel 1 05c h 09 h sfrpage special function register page register 080 h 00 h table 2 register overview and reset value (cont?d) register short name re gister long name offset address reset value TDA5235 appendix register overview data sheet 175 v1.0, 2010-02-19 ppcfg0 pp0 and pp1 configuration register 081 h 50 h ppcfg1 pp2 and pp3 configuration register 082 h 12 h ppcfg2 ppx port configuration register 083 h 00 h rxruncfg0 rx run configuration register 0 084 h ff h rxruncfg1 rx run configuration register 1 085 h ff h clkout0 clock divider register 0 086 h 0b h clkout1 clock divider register 1 087 h 00 h clkout2 clock divider register 2 088 h 00 h rfc rf control register 089 h 07 h bpfcalcfg0 bpf calibration configuration register 0 08a h 07 h bpfcalcfg1 bpf calibration configuration register 1 08b h 04 h xtalcal0 xtal coarse calibration register 08c h 10 h xtalcal1 xtal fine calibration register 08d h 00 h rssimonc rssi monitor configuration register 08e h 01 h adcinsel adc input selection register 08f h 00 h rssioffs rssi offset register 090 h 80 h rssislope rssi slope register 091 h 80 h cdrdrthrp cdr data rate acceptance positive threshold register 092 h 1e h cdrdrthrn cdr data rate acceptance negative threshold register 093 h 23 h im0 interrupt mask register 0 094 h 00 h spmap self polling mode active periods register 096 h 01 h spmip self polling mode idle periods register 097 h 01 h spmc self polling mode control register 098 h 00 h spmrt self polling mode reference timer register 099 h 01 h spmofft0 self polling mode off time register 0 09a h 01 h spmofft1 self polling mode off time register 1 09b h 00 h spmonta0 self polling mode on time config a register 0 09c h 01 h spmonta1 self polling mode on time config a register 1 09d h 00 h spmontb0 self polling mode on time config b register 0 09e h 01 h spmontb1 self polling mode on time config b register 1 09f h 00 h extpcmd external processing command register 0a4 h 00 h cmc1 chip mode control register 1 0a5 h 04 h cmc0 chip mode control register 0 0a6 h 10 h rssipwu wakeup peak detector readout register 0a7 h 00 h is0 interrupt status register 0 0a8 h ff h rfpllacc rf pll actual channel and configuration register 0aa h 00 h table 2 register overview and reset value (cont?d) register short name re gister long name offset address reset value TDA5235 appendix register overview data sheet 176 v1.0, 2010-02-19 rssiprx rssi peak detector readout register 0ab h 00 h rssippl rssi payload peak detector readout register 0ac h 00 h pldlen payload data length register 0ad h 00 h adcresh adc result high byte register 0ae h 00 h adcresl adc result low byte register 0af h 00 h vacres vco autocalibration result readout register 0b0 h 00 h afcoffset afc offset read register 0b1 h 00 h agcgainr agc gain readout register 0b2 h 00 h spiat spi address tracer register 0b3 h 00 h spidt spi data tracer register 0b4 h 00 h spichksum spi checksum register 0b5 h 00 h sn0 serial number register 0 0b6 h 00 h sn1 serial number register 1 0b7 h 00 h sn2 serial number register 2 0b8 h 00 h sn3 serial number register 3 0b9 h 00 h rssirx rssi readout register 0ba h 00 h rssipmf rssi peak memory filter readout register 0bb h 00 h spwr signal power readout register 0bc h 00 h npwr noise power readout register 0bd h 00 h b_mid0 message id register 0 100 h 00 h b_mid1 message id register 1 101 h 00 h b_mid2 message id register 2 102 h 00 h b_mid3 message id register 3 103 h 00 h b_mid4 message id register 4 104 h 00 h b_mid5 message id register 5 105 h 00 h b_mid6 message id register 6 106 h 00 h b_mid7 message id register 7 107 h 00 h b_mid8 message id register 8 108 h 00 h b_mid9 message id register 9 109 h 00 h b_mid10 message id register 10 10a h 00 h b_mid11 message id register 11 10b h 00 h b_mid12 message id register 12 10c h 00 h b_mid13 message id register 13 10d h 00 h b_mid14 message id register 14 10e h 00 h b_mid15 message id register 15 10f h 00 h b_mid16 message id register 16 110 h 00 h b_mid17 message id register 17 111 h 00 h b_mid18 message id register 18 112 h 00 h table 2 register overview and reset value (cont?d) register short name re gister long name offset address reset value TDA5235 appendix register overview data sheet 177 v1.0, 2010-02-19 b_mid19 message id register 19 113 h 00 h b_midc0 message id control register 0 114 h 00 h b_midc1 message id control register 1 115 h 00 h b_if1 if1 register 116 h 20 h b_wuc wake-up control register 117 h 04 h b_wupat0 wake-up pattern register 0 118 h 00 h b_wupat1 wake-up pattern register 1 119 h 00 h b_wubcnt wake-up bit or chip count register 11a h 00 h b_wurssith1 rssi wake-up threshold for channel 1 register 11b h 00 h b_wurssibl1 rssi wake-up blocking level low channel 1 register 11c h ff h b_wurssibh1 rssi wake-up blocking level high channel 1 register 11d h 00 h b_sigdetsat signal detector saturation threshold register 124 h 10 h b_wulot wake-up on level observation time register 125 h 00 h b_sysrcto synchronization search time-out register 126 h 87 h b_totim_sync sync timeout timer register 127 h ff h b_totim_tsi tsi timeout timer register 128 h 00 h b_totim_eom eom timeout timer register 129 h 00 h b_afclimit afc limit configuration register 12a h 02 h b_afcagcd afc/agc freeze delay register 12b h 00 h b_afcsfcfg afc start/freeze configuration register 12c h 00 h b_afck1cfg0 afc integrator 1 gain register 0 12d h 00 h b_afck1cfg1 afc integrator 1 gain register 1 12e h 00 h b_afck2cfg0 afc integrator 2 gain register 0 12f h 00 h b_afck2cfg1 afc integrator 2 gain register 1 130 h 00 h b_pmfudsf peak memory filter up-down factor register 131 h 42 h b_agcsfcfg agc start/freeze configuration register 132 h 00 h b_agccfg0 agc configuration register 0 133 h 2b h b_agccfg1 agc configuration register 1 134 h 03 h b_agcthr agc threshold register 135 h 08 h b_digrxc digital receiver configuration register 136 h 40 h b_pkbitpos rssi peak detector bit position register 137 h 00 h b_isupfcsel image supression fc selection register 138 h 07 h b_pdecf pre decimation factor register 139 h 00 h b_pdecscfsk pre decimation scaling register fsk mode 13a h 00 h b_pdecscask pre decimation scaling register ask mode 13b h 20 h b_mfc matched filter control register 13c h 07 h b_src sampe rate converter nco tune 13d h 00 h table 2 register overview and reset value (cont?d) register short name re gister long name offset address reset value TDA5235 appendix register overview data sheet 178 v1.0, 2010-02-19 b_extslc externel data slicer configuration 13e h 02 h b_sigdet0 signal detector threshold level register - run mode 13f h 00 h b_sigdet1 signal detector threshold level register - wakeup 140 h 00 h b_sigdetlo signal detector threshold low level register 141 h 00 h b_sigdetsel signal detector range selection register 142 h 7f h b_sigdetcfg signal detector configuration register 143 h 00 h b_ndthres fsk noise detector threshold register 144 h 00 h b_ndconfig fsk noise detector configuration register 145 h 07 h b_cdrp clock and data recovery p configuration register 146 h e6 h b_cdri clock and data recovery configuration register 147 h 65 h b_cdrri clock and data recovery runin configuration register 148 h 01 h b_cdrtolc cdr dc chip tolerance register 149 h 0c h b_cdrtolb cdr dc bit tolerance register 14a h 1e h b_tvwin timing violation window register 14b h 28 h b_slccfg slicer configuration register 14c h 90 h b_tsimode tsi detection mode register 14d h 80 h b_tsilena tsi length register a 14e h 00 h b_tsilenb tsi length register b 14f h 00 h b_tsigap tsi gap length register 150 h 00 h b_tsipta0 tsi pattern data reference a register 0 151 h 00 h b_tsipta1 tsi pattern data reference a register 1 152 h 00 h b_tsiptb0 tsi pattern data reference b register 0 153 h 00 h b_tsiptb1 tsi pattern data reference b register 1 154 h 00 h b_eomc end of message control register 155 h 05 h b_eomdlen eom data length limit register 156 h 00 h b_eomdlenp eom data length limit parallel mode register 157 h 00 h b_chcfg channel configuration register 158 h 04 h b_pllintc1 pll mmd integer value register channel 1 159 h 93 h b_pllfrac0c1 pll fractional division ratio register 0 channel 1 15a h f3 h b_pllfrac1c1 pll fractional division ratio register 1 channel 1 15b h 07 h b_pllfrac2c1 pll fractional division ratio register 2 channel 1 15c h 09 h table 2 register overview and reset value (cont?d) register short name re gister long name offset address reset value TDA5235 appendix register description data sheet 179 v1.0, 2010-02-19 register description message id register 0 message id register 1 message id register 2 a_mid0 offset reset value message id register 0 000 h 00 h field bits type description mid0 7:0 w message id register 0 reset: 00 h a_mid1 offset reset value message id register 1 001 h 00 h field bits type description mid1 7:0 w message id register 1 reset: 00 h a_mid2 offset reset value message id register 2 002 h 00 h z 0 , ' z 0 , ' TDA5235 appendix register description data sheet 180 v1.0, 2010-02-19 message id register 3 message id register 4 message id register 5 field bits type description mid2 7:0 w message id register 2 reset: 00 h a_mid3 offset reset value message id register 3 003 h 00 h field bits type description mid3 7:0 w message id register 3 reset: 00 h a_mid4 offset reset value message id register 4 004 h 00 h field bits type description mid4 7:0 w message id register 4 reset: 00 h z 0 , ' z 0 , ' z 0 , ' TDA5235 appendix register description data sheet 181 v1.0, 2010-02-19 message id register 6 message id register 7 a_mid5 offset reset value message id register 5 005 h 00 h field bits type description mid5 7:0 w message id register 5 reset: 00 h a_mid6 offset reset value message id register 6 006 h 00 h field bits type description mid6 7:0 w message id register 6 reset: 00 h a_mid7 offset reset value message id register 7 007 h 00 h field bits type description mid7 7:0 w message id register 7 reset: 00 h z 0 , ' z 0 , ' z 0 , ' TDA5235 appendix register description data sheet 182 v1.0, 2010-02-19 message id register 8 message id register 9 message id register 10 a_mid8 offset reset value message id register 8 008 h 00 h field bits type description mid8 7:0 w message id register 8 reset: 00 h a_mid9 offset reset value message id register 9 009 h 00 h field bits type description mid9 7:0 w message id register 9 reset: 00 h a_mid10 offset reset value message id register 10 00a h 00 h z 0 , ' z 0 , ' z 0 , ' TDA5235 appendix register description data sheet 183 v1.0, 2010-02-19 message id register 11 message id register 12 message id register 13 field bits type description mid10 7:0 w message id register 10 reset: 00 h a_mid11 offset reset value message id register 11 00b h 00 h field bits type description mid11 7:0 w message id register 11 reset: 00 h a_mid12 offset reset value message id register 12 00c h 00 h field bits type description mid12 7:0 w message id register 12 reset: 00 h a_mid13 offset reset value message id register 13 00d h 00 h z 0 , ' z 0 , ' TDA5235 appendix register description data sheet 184 v1.0, 2010-02-19 message id register 14 message id register 15 message id register 16 field bits type description mid13 7:0 w message id register 13 reset: 00 h a_mid14 offset reset value message id register 14 00e h 00 h field bits type description mid14 7:0 w message id register 14 reset: 00 h a_mid15 offset reset value message id register 15 00f h 00 h field bits type description mid15 7:0 w message id register 15 reset: 00 h z 0 , ' z 0 , ' z 0 , ' TDA5235 appendix register description data sheet 185 v1.0, 2010-02-19 message id register 17 message id register 18 a_mid16 offset reset value message id register 16 010 h 00 h field bits type description mid16 7:0 w message id register 16 reset: 00 h a_mid17 offset reset value message id register 17 011 h 00 h field bits type description mid17 7:0 w message id register 17 reset: 00 h a_mid18 offset reset value message id register 18 012 h 00 h field bits type description mid18 7:0 w message id register 18 reset: 00 h z 0 , ' z 0 , ' z 0 , ' TDA5235 appendix register description data sheet 186 v1.0, 2010-02-19 message id register 19 message id control register 0 message id control register 1 a_mid19 offset reset value message id register 19 013 h 00 h field bits type description mid19 7:0 w message id register 19 reset: 00 h a_midc0 offset reset value message id control register 0 014 h 00 h field bits type description unused 7 - unused reset: 0 h sspos 6:0 w message id scan start position min: 00h = comparision starts one bit after fsync max: 7f = comparision starts 128 bits after fsync reset: 00 h a_midc1 offset reset value message id control register 1 015 h 00 h z 0 , ' 8 1 8 6 ( ' z 6 6 3 2 6 TDA5235 appendix register description data sheet 187 v1.0, 2010-02-19 if1 register field bits type description unused 7:4 - unused reset: 0 h midsen 3 w enable message id screening 0 b disabled 1 b enabled reset: 0 h midbo 2 w message id byte organisation 0 b 2 byte mode 1 b 4 byte mode reset: 0 h midnts 1:0 w message id number of bytes to scan (4 byte mode / 2 byte mode) 00 b 1 byte to scan / 1 byte to scan 01 b 2 bytes to scan / 2 bytes to scan 10 b 3 bytes to scan / 2 bytes to scan 11 b 4 bytes to scan / 2 bytes to scan reset: 0 h a_if1 offset reset value if1 register 016 h 20 h field bits type description unused 7 - unused reset: 0 h ssbsel 6 w rxrf receive side band select 0 b rf = lo + if1 (lo-side lo-injection) 1 b rf = lo - if1 (hi-side lo-injection) reset: 0 h 8 1 8 6 ( ' z 0 , ' 6 ( 1 z 0 , ' % 2 z 0 , ' 1 7 6 8 1 8 6 ( ' z 6 6 % 6 ( / z % 3 ) % : 6 ( / z 6 ' & 6 ( / z , ) % 8 ) ( 1 z & ( 5 ) 6 ( / TDA5235 appendix register description data sheet 188 v1.0, 2010-02-19 wake-up control register bpfbwsel 5:3 w band pass filter bandwidth selection 000 b 50 khz 001 b 80 khz 010 b 125 khz 011 b 200 khz 100 b 300 khz 101 b not used 110 b not used 111 b not used reset: 4 h sdcsel 2 w single / double conversion selection 0 b double conversion (10.7 mhz/274 khz) 1 b single conversion (274 khz) reset: 0 h ifbufen 1 w if buffer enable 0 b disabled 1 b enabled reset: 0 h cerfsel 0 w number of external ceramic filters 0 b 1 ceramic filter 1 b 2 ceramic filters reset: 0 h a_wuc offset reset value wake-up control register 017 h 04 h field bits type description unused 7 - unused reset: 0 h pwuen 6 w parallel wake up mode enable this feature can only be used, when modulation type is the same for spm and rmsp 0 b disabled 1 b enabled reset: 0 h field bits type description 8 1 8 6 ( ' z 3 : 8 ( 1 z : 8 3 0 6 ( / z : 8 / & 8 ) ) % z 8 ) ) % / & 2 2 z : 8 & 5 7 TDA5235 appendix register description data sheet 189 v1.0, 2010-02-19 wake-up pattern register 0 wupmsel 5 w wake up pattern mode selection 0 b chip mode 1 b bit mode reset: 0 h wulcuffb 4 w select a "wake up on level criterion", when uffblcoo is enabled. 0 b rssi automatically selected, when a_chcfg.extproc = "10" 1 b signal recognition reset: 0 h uffblcoo 3 w ultrafast fall back to sleep or additional level criterion in constant on off. enables additional parallel processing of "level criterion", when a "data criterion" is selected in wucrt. in case of fast fall back to sleep or permanent wake-up search, this mode is called uffb (ultrafast fall back). same mode can be used in constant on-off. 0 b disabled 1 b enabled reset: 0 h wucrt 2:0 w select a "wake up criterion" 000 b pattern detection (data criterion) when a_chcfg.extroc = "01" this setting is mapped to 0x3 001 b random bits (data criterion) when a_chcfg.extroc = "01" this setting is mapped to 0x3 010 b equal bits (data criterion) when a_chcfg.extroc = "01" this setting is mapped to 0x3 011 b wake up on symbol sync, valid data rate (data criterion); the a_wubcnt register is not used in this mode 100 b rssi (level criterion) automatically selected, when a_chcfg.extproc = "10" 101 b signal recognition (level criterion) 110 b n.u. 111 b n.u. reset: 4 h a_wupat0 offset reset value wake-up pattern register 0 018 h 00 h field bits type description z : 8 3 $ 7 TDA5235 appendix register description data sheet 190 v1.0, 2010-02-19 wake-up pattern register 1 wake-up bit or chip count register field bits type description wupat0 7:0 w wake up detection pattern: bit 7...bit 0(lsb) (in bits/chips) reset: 00 h a_wupat1 offset reset value wake-up pattern register 1 019 h 00 h field bits type description wupat1 7:0 w wake up detection pattern: (msb) bit 15...bit 8 (in bits/chips) reset: 00 h a_wubcnt offset reset value wake-up bit or chip count register 01a h 00 h field bits type description unused 7 - unused reset: 0 h z : 8 3 $ 7 8 1 8 6 ( ' z : 8 % & 1 7 TDA5235 appendix register description data sheet 191 v1.0, 2010-02-19 rssi wake-up threshold for channel 1 register rssi wake-up blocking level low channel 1 register wubcnt 6:0 w wake up bit/chip count register (unit is bits; only exception is wu pattern chip mode, where unit is chips, see a_wuc.wupmsel) counter register to define the maximum counts of bits/chips for wake up detection. min: 00h = 0 bits/chips to count in random bits or equal bits mode this will cause a wake up on data criterion immediately after symbol synchronization is found. in pattern detection mode this will cause no wake up on data criterion. in this mode there is needed minimum 11h = 17 bits/chips to shift one pattern through the whole pattern detector. because comparision can only be started when at least the comparision register is completely filled. max: 7fh: 127 bits/chips to count after symbol sync found reset: 00 h a_wurssith1 offset reset value rssi wake-up threshold for channel 1 register 01b h 00 h field bits type description wurssith1 7:0 w wake up on rssi threshold level for channel 1 wake up request generated when actual rssi level is above this threshold reset: 00 h a_wurssibl1 offset reset value rssi wake-up blocking level low channel 1 register 01c h ff h field bits type description z : 8 5 6 6 , 7 + TDA5235 appendix register description data sheet 192 v1.0, 2010-02-19 rssi wake-up blocking level high channel 1 register signal detector saturation threshold register field bits type description wurssibl1 7:0 w wake up on rssi blocking level low for channel 1 reset: ff h a_wurssibh1 offset reset value rssi wake-up blocking level high channel 1 register 01d h 00 h field bits type description wurssibh1 7:0 w wake up on rssi blocking level high for channel 1, when rssi is selected as wu criterion or ffb criterion. in case of signal recognition as wu criterion or ffb criterion, the register defines the minimum consecutive t/16 samples of the signal recognition output to be at high level for a positive wake up event generation or ffb generation reset: 00 h a_sigdetsat offset reset value signal detector saturation threshold register 024 h 10 h z : 8 5 6 6 , % / z : 8 5 6 6 , % + z 6 , * ' ( 7 6 $ 7 TDA5235 appendix register description data sheet 193 v1.0, 2010-02-19 wake-up on level observation time register synchronization search time-out register field bits type description sigdetsat 7:0 w saturation threshold of the sigdet peak detector used for zero-tube threshold calculation. reset: 10 h a_wulot offset reset value wake-up on level observation time register 025 h 00 h field bits type description wulotps 7:5 w wake-up level observation time prescaler 000 b 4 001 b 8 010 b 16 011 b 32 100 b 64 101 b 128 110 b 256 111 b 512 reset: 0 h wulot 4:0 w wake-up level observation time min. 01h : twulot = 1 * wulotps * 64 / fsys max 1fh : twulot = 31 * wulotps * 64 / fsys value 00h : twulot = 32 * wulotps * 64 / fsys reset: 00 h a_sysrcto offset reset value synchronization search time-out register 026 h 87 h z : 8 / 2 7 3 6 z : 8 / 2 7 z 6 < 6 5 & 7 2 TDA5235 appendix register description data sheet 194 v1.0, 2010-02-19 sync timeout timer register tsi timeout timer register field bits type description sysrcto 7:0 w synchronization search time out ffh: 15 15/16 bit 00h: 0 bit reset: 87 h a_totim_sync offset reset value sync timeout timer register 027 h ff h field bits type description totimsync 7:0 w set value of time-out timer (symbol synchronization) timer is used to get back from run mode self polling to the self polling mode whenever there is no symbol synchronization. timer is set back at new cycle start of run mode self polling. timeout= (totimsync * 64 * 512) / fsys min: 01h = (1 * 64 * 512)/ fsys max: ffh= (255 * 64 * 512) / fsys 00h: disabled reset: ff h a_totim_tsi offset reset value tsi timeout timer register 028 h 00 h z 7 2 7 , 0 6 < 1 & z 7 2 7 , 0 7 6 , TDA5235 appendix register description data sheet 195 v1.0, 2010-02-19 eom timeout timer register afc limit configuration register field bits type description totimtsi 7:0 w set value of time-out timer (telegram start identifier) timer is used to get back from run mode self polling to the self polling mode whenever a symbol synchronisation is available but there is no tsi detected. timer is set back at new cycle start of run mode self polling. timeout= (totimtsi * 64 * 512) / fsys min: 01h = (1 * 64 * 512)/ fsys max: ffh= (255 * 64 * 512) / fsys 00h: disabled reset: 00 h a_totim_eom offset reset value eom timeout timer register 029 h 00 h field bits type description totimeom 7:0 w set value of time-out timer (end of message) timer is used to get back from run mode self polling to the self polling mode whenever a tsi has been detected but there is no eom detected. timer is set back at new cycle start of run mode self polling. timeout= (totimeom * 64 * 512 * 2) / fsys min: 01h = (1 * 64 * 512 * 2)/ fsys max: ffh= (255 * 64 * 512 * 2) / fsys 00h: disabled reset: 00 h a_afclimit offset reset value afc limit configuration register 02a h 02 h z 7 2 7 , 0 ( 2 0 8 1 8 6 ( ' z $ ) & / , 0 , 7 TDA5235 appendix register description data sheet 196 v1.0, 2010-02-19 afc/agc freeze delay register afc start/freeze configuration register field bits type description unused 7:4 - unused reset: 0 h afclimit 3:0 w afc frequency offset saturation limit ==> 1...15 x 21.4 khz min: 1h = +/- fsys / 2^(22-12) hz max: fh = +/- 15 * fsys / 2^(22-12) hz reg. value 0h = 0 hz - no afc correction reset: 2 h a_afcagcd offset reset value afc/agc freeze delay register 02b h 00 h field bits type description afcagcd 7:0 w afc/agc freeze delay counter division ratio the base period for the delay counter is the 8-16 samples/chip (predecimation strobe) divided by 4 reset: 00 h a_afcsfcfg offset reset value afc start/freeze configuration register 02c h 00 h field bits type description unused 7 - unused reset: 0 h z $ ) & $ * & ' 8 1 8 6 ( ' z $ ) & % / $ 6 . z $ ) & 5 ( 6 $ 7 & & z $ ) & ) 5 ( ( = ( z $ ) & 6 7 $ 5 7 TDA5235 appendix register description data sheet 197 v1.0, 2010-02-19 afc integrator 1 gain register 0 afcblask 6 w afc blocking during a low phase in the ask signal 0 b disabled 1 b enabled reset: 0 h afcresatc c 5 w enable afc restart at the beginning of the current configuration in self polling mode and at leaving the hold state (when bit cmc0.initpllhold is set) in run mode slave 0 b disabled 1 b enabled reset: 0 h afcfreeze 4:2 w afc freeze configuration when selecting a level criterion here, please note to use the same level criterion as for wake-up 000 b stay on 001 b freeze on rssi event + delay (afcagcdel) 010 b freeze on signal recognition event + delay (afcagcdel) 011 b freeze on symbol synchronization + delay (afcagcdel) 100 b spi command - write to extpcmd.afcmanf bit 101 b n.u. 110 b n.u. 111 b n.u. reset: 0 h afcstart 1:0 w afc start configuration when selecting a level criterion here, please note to use the same level criterion as for wake-up 00 b off 01 b direct on 10 b start on rssi event 11 b start on signal recognition event reset: 0 h a_afck1cfg0 offset reset value afc integrator 1 gain register 0 02d h 00 h field bits type description z $ ) & . b TDA5235 appendix register description data sheet 198 v1.0, 2010-02-19 afc integrator 1 gain register 1 afc integrator 2 gain register 0 afc integrator 2 gain register 1 field bits type description afck1_0 7:0 w afc filter coefficient k1, afck1(11:0) = afck1_1(msb) & afck1_0(lsb) reset: 00 h a_afck1cfg1 offset reset value afc integrator 1 gain register 1 02e h 00 h field bits type description unused 7:4 - unused reset: 0 h afck1_1 3:0 w afc filter coefficient k1, afck1(11:0) = afck1_1(msb) & afck1_0(lsb) reset: 0 h a_afck2cfg0 offset reset value afc integrator 2 gain register 0 02f h 00 h field bits type description afck2_0 7:0 w afc filter coefficient k2, afck2(11:0) = afck2_1(msb) & afck2_0(lsb) reset: 00 h 8 1 8 6 ( ' z $ ) & . b z $ ) & . b TDA5235 appendix register description data sheet 199 v1.0, 2010-02-19 peak memory filter up-down factor register a_afck2cfg1 offset reset value afc integrator 2 gain register 1 030 h 00 h field bits type description unused 7:4 - unused reset: 0 h afck2_1 3:0 w afc filter coefficient k2, afck2(11:0) = afck2_1(msb) & afck2_0(lsb) reset: 0 h a_pmfudsf offset reset value peak memory filter up-down factor register 031 h 42 h field bits type description unused 7 - unused reset: 0 h pmfup 6:4 w peak memory filter attack (up) factor 000 b 2^-1 001 b 2^-2 010 b 2^-3 011 b 2^-4 100 b 2^-5 101 b 2^-6 110 b 2^-7 111 b 2^-8 reset: 4 h unused 3 - unused reset: 0 h 8 1 8 6 ( ' z $ ) & . b 8 1 8 6 ( ' z 3 0 ) 8 3 8 1 8 6 ( ' z 3 0 ) ' 1 TDA5235 appendix register description data sheet 200 v1.0, 2010-02-19 agc start/freeze configuration register pmfdn 2:0 w peak memory filter decay (down) factor (additional to attack factor) 000 b 2^-2 001 b 2^-3 010 b 2^-4 011 b 2^-5 100 b 2^-6 101 b 2^-7 110 b 2^-8 111 b 2^-9 reset: 2 h a_agcsfcfg offset reset value agc start/freeze configuration register 032 h 00 h field bits type description unused 7:6 - unused reset: 0 h agcresatc c 5 w enable agc restart at the beginning of the current configuration in self polling mode and at leaving the hold state (when bit cmc0.initpllhold is set) in run mode slave 0 b disabled 1 b enabled reset: 0 h agcfreeze 4:2 w agc freeze configuration when selecting a level criterion here, please note to use the same level criterion as for wake-up 000 b stay on 001 b freeze on rssi event + delay (afcagcdel) 010 b freeze on signal recognition event + delay (afcagcdel) 011 b freeze on symbol synchronization + delay (afcagcdel) 100 b spi command - write to extpcmd.agcmanf bit 101 b n.u. 110 b n.u. 111 b n.u. reset: 0 h field bits type description 8 1 8 6 ( ' z $ * & 5 ( 6 $ 7 & & z $ * & ) 5 ( ( = ( z $ * & 6 7 $ 5 7 TDA5235 appendix register description data sheet 201 v1.0, 2010-02-19 agc configuration register 0 agcstart 1:0 w agc start configuration when selecting a level criterion here, please note to use the same level criterion as for wake-up 00 b off 01 b direct on 10 b start on rssi event 11 b start on signal recognition event reset: 0 h a_agccfg0 offset reset value agc configuration register 0 033 h 2b h field bits type description unused 7 - unused reset: 0 h agcdgc 6:4 w agc digital rssi gain correction tuning 000 b 14.5 db 001 b 15.0 db 010 b 15.5 db 011 b 16.0 db 100 b 16.5 db 101 b 17.0 db 110 b 17.5 db 111 b 18.0 db reset: 2 h agchys 3:2 w agc threshold hysteresis 00 b 12.8 db 01 b 17.1 db 10 b 21.3 db 11 b 25.6 db reset: 2 h agcgain 1:0 w agc gain control 00 b 0 db 01 b -15 db 10 b -30 db 11 b automatic reset: 3 h field bits type description 8 1 8 6 ( ' z $ * & ' * & z $ * & + < 6 z $ * & * $ , 1 TDA5235 appendix register description data sheet 202 v1.0, 2010-02-19 agc configuration register 1 agc threshold register digital receiver configuration register a_agccfg1 offset reset value agc configuration register 1 034 h 03 h field bits type description unused 7:2 - unused reset: 00 h agcthoffs 1:0 w agc threshold offset 00 b 25.5 db 01 b 38.3 db 10 b 51.1 db 11 b 63.9 db reset: 3 h a_agcthr offset reset value agc threshold register 035 h 08 h field bits type description agctup 7:4 w agc upper attack threshold [db] agc upper threshold = a_agccfg1.agcthoffs + 25.6 + agctup*1.6 reset: 0 h agctlo 3:0 w agc lower attack threshold [db] agc lower threshold = a_agccfg1.agcthoffs + agctlo*1.6 reset: 8 h 8 1 8 6 ( ' z $ * & 7 + 2 ) ) 6 z $ * & 7 8 3 z $ * & 7 / 2 TDA5235 appendix register description data sheet 203 v1.0, 2010-02-19 a_digrxc offset reset value digital receiver configuration register 036 h 40 h field bits type description initdrxes 7 w init the digital receiver at eom or loss of symbol sync (e.g. for initialization of the peak memory filter) 0 b disabled 1 b enabled reset: 0 h initfrcs 6 w init the framer at cycle start in rmsp. if disabled, the wup data can be used as part of tsi as well in case the modulation type is the same for spm and rmsp 0 b disabled 1 b enabled reset: 1 h code 5:4 w encoding mode selection 00 b manchester code 01 b differential manchester code 10 b biphase space 11 b biphase mark reset: 0 h chipdinv 3 w baseband chip data inversion for ch_data and decoder/framer input. therefore inverted manchester and inverted differential manchester can be decoded internally. 0 b not inverted 1 b inverted reset: 0 h dinvext 2 w data inversion of signal data and data_matchfil for external processing 0 b not inverted 1 b inverted reset: 0 h aafbyp 1 w anti-alliasing filter bypass for rssi pin 0 b not bypassed 1 b bypassed reset: 0 h aaffcsel 0 w anti-alliasing filter co rner frequency select 0 b 40 khz 1 b 80 khz reset: 0 h z , 1 , 7 ' 5 ; ( 6 z , 1 , 7 ) 5 & 6 z & 2 ' ( z & + , 3 ' , 1 9 z ' , 1 9 ( ; 7 z $ $ ) % < 3 z $ $ ) ) & 6 ( / TDA5235 appendix register description data sheet 204 v1.0, 2010-02-19 rssi peak detector bit position register image supression fc selection register a_pkbitpos offset reset value rssi peak detector bit position register 037 h 00 h field bits type description rssidly 7:0 w rssi detector start-up delay for rssippl register min: 00h: 0 bit delay (start with first bit after fsync) max: ffh: 255 bit delay note: due to filtering and signal computation, the latency t1 and t2 have to be added reset: 00 h a_isupfcsel offset reset value image supression fc selection register 038 h 07 h field bits type description unused 7:4 - unused reset: 0 h fcsel 2:0 w image supression filter corner frequency selection for fsk signal path 000 b 33 khz 001 b 46 khz 010 b 65 khz 011 b 93 khz 100 b 132 khz 101 b 190 khz 110 b 239 khz 111 b 282 khz reset: 7 h z 5 6 6 , ' / < 8 1 8 6 ( ' 5 h v z ) & 6 ( / TDA5235 appendix register description data sheet 205 v1.0, 2010-02-19 pre decimation factor register pre decimation scaling register fsk mode pre decimation scaling register ask mode a_pdecf offset reset value pre decimation factor register 039 h 00 h field bits type description unused 7 - unused reset: 0 h predecf 6:0 w predecimation filter decimation factor predecimation factor = predecf + 1 reset: 00 h a_pdecscfsk offset reset value pre decimation scaling register fsk mode 03a h 00 h field bits type description intpolenf 5 w fsk data interpolation enable 0 b disabled 1 b enabled reset: 0 h pdscalef 4:0 w predecimation block scaling factor for fsk min 00h : 2^-10 max 17h : 2^13 reset: 00 h 8 1 8 6 ( ' z 3 5 ( ' ( & ) 5 h v z , 1 7 3 2 / ( 1 ) z 3 ' 6 & $ / ( ) TDA5235 appendix register description data sheet 206 v1.0, 2010-02-19 matched filter control register sampe rate converter nco tune a_pdecscask offset reset value pre decimation scaling register ask mode 03b h 20 h field bits type description unused 7 - unused reset: 0 h intpolena 5 w ask data interpolation enable 0 b disabled 1 b enabled reset: 1 h pdscalea 4:0 w predecimation block scaling factor for ask min 00h : 2^-10 max 17h : 2^13 reset: 00 h a_mfc offset reset value matched filter control register 03c h 07 h field bits type description unused 7:4 - unused reset: 0 h mfl 3:0 w matched filter length mf length = mfl + 1 reset: 7 h a_src offset reset value sampe rate converter nco tune 03d h 00 h 8 1 8 6 ( ' 5 h v z , 1 7 3 2 / ( 1 $ z 3 ' 6 & $ / ( $ 8 1 8 6 ( ' z 0 ) / TDA5235 appendix register description data sheet 207 v1.0, 2010-02-19 externel data slicer configuration signal detector threshold level register - run mode field bits type description srcnco 7:0 w sample rate converter nco tune min 00h : fout = fin max ffh : fout = fin / 2 reset: 00 h a_extslc offset reset value externel data slicer configuration 03e h 02 h field bits type description unused 7 - unused reset: 0 h eslcsca 4:3 w external slicer bw selection scaling 00 b 1/2 01 b 1/4 10 b 1/8 11 b 1/16 reset: 0 h eslcbw 2:0 w external slicer manual bw selection 000 b 1/8 001 b 1/16 010 b 1/24 011 b 1/32 100 b 1/40 101 b 1/48 110 b n.u. 111 b n.u. reset: 2 h z 6 5 & 1 & 2 8 1 8 6 ( ' 5 h v z ( 6 / & 6 & $ z ( 6 / & % : TDA5235 appendix register description data sheet 208 v1.0, 2010-02-19 signal detector threshold level register - wakeup signal detector threshold low level register a_sigdet0 offset reset value signal detector threshold level register - run mode 03f h 00 h field bits type description sdthr 7:0 w signal detector threshold level for run mode reset: 00 h a_sigdet1 offset reset value signal detector threshold level register - wakeup 040 h 00 h field bits type description sdthr 7:0 w signal detector threshold level for wakeup reset: 00 h a_sigdetlo offset reset value signal detector threshold low level register 041 h 00 h z 6 ' 7 + 5 z 6 ' 7 + 5 z 6 ' / 2 7 + 5 TDA5235 appendix register description data sheet 209 v1.0, 2010-02-19 signal detector range selection register field bits type description sdlothr 7:0 w signal detector threshold low level. this threshold level is only valid, if the fsk noise detector selection in the a_ndconfig register is set to 11b reset: 00 h a_sigdetsel offset reset value signal detector range selection register 042 h 7f h field bits type description sdrselask 5:4 w a_sigdet0/1 range selection factor for ask. the selected signal detector value is multiplied by the 2^range selection factor. use the right setting to fit the measured spwr value. 00 b 6 01 b 7 10 b 7+6 11 b 8 reset: 3 h sdrselfsk 3:2 w a_sigdet0/1 range selection factor for fsk. the selected signal detector value is multiplied by the 2^range selection factor. use the right setting to fit the measured spwr value. 00 b 2 01 b 4 10 b 6 11 b 8 reset: 3 h sdlorsel 1:0 w sigdetlo range selection factor. the selected signal detector value is multiplied by the 2^rang e selection factor. use the right setting to fit the measured spwr value. 00 b 2 01 b 4 10 b 6 11 b 8 reset: 3 h 5 h v z 6 ' 5 6 ( / $ 6 . z 6 ' 5 6 ( / ) 6 . z 6 ' / 2 5 6 ( / TDA5235 appendix register description data sheet 210 v1.0, 2010-02-19 signal detector configuration register fsk noise detector threshold register a_sigdetcfg offset reset value signal detector configuration register 043 h 00 h field bits type description unused 7:4 - unused reset: 0 h sdlore 2 w source selection of signal power readout register 0 b signal power for a_sigdet0/1 1 b signal for minimal usable fsk deviation, the sigdet low level can be read out with spwr register reset: 0 h sdcnt1 1 w signal detector threshold counter for wakeup 0 b disabled 1 b 1/2 bit reset: 0 h sdcnt0 0 w signal detector threshold counter for run mode 0 b disabled 1 b 1/2 bit reset: 0 h a_ndthres offset reset value fsk noise detector threshold register 044 h 00 h field bits type description ndthres 7:0 w fsk noise detector threshold reset: 00 h 8 1 8 6 ( ' 5 h v z 6 ' / 2 5 ( z 6 ' & 1 7 z 6 ' & 1 7 z 1 ' 7 + 5 ( 6 TDA5235 appendix register description data sheet 211 v1.0, 2010-02-19 fsk noise detector configuration register clock and data recovery p configuration register a_ndconfig offset reset value fsk noise detector configuration register 045 h 07 h field bits type description ndrsel 7:6 w fsk noise detector range selection 00 b 2^7 01 b 2^6 10 b 2^5 11 b 2^4 reset: 0 h ndsel 5:4 w signal and noise detector selection 00 b signal detection (=squelch) only. this mode is recommended for ask. 01 b noise detection only 10 b signal and noise detection simultaneously 11 b signal and noise detection simultaneously, but the fsk noise detect signal is valid only if the sigdetlo threshold is exceeded. this is the recommended mode for fsk. reset: 0 h ndtl 3:2 w fsk noise detector threshold level 00 b 1/2 01 b 3/8 10 b 1/4 11 b 1/8 reset: 1 h ndpdsr 1:0 w fsk noise detector - peak detector slew rate 00 b 1/256 01 b 1/128 10 b 1/64 11 b 1/32 reset: 3 h a_cdrp offset reset value clock and data recovery p configuration register 046 h e6 h z 1 ' 5 6 ( / z 1 ' 6 ( / z 1 ' 7 / z 1 ' 3 ' 6 5 TDA5235 appendix register description data sheet 212 v1.0, 2010-02-19 clock and data recovery configuration register field bits type description pdsr 7:6 w peak-detector slew rate. the slew rate of the peak-detector in the clock-recovery path will be set with pdsr. actually, peak-detector part of signal detector block 00 b up/down = 1/64 01 b up = 1/64; down = 1/128 10 b up = 1/32; down = 1/128 11 b up = 1/32; down = 1/256 reset: 3 h phden1 5 w phase detector error (pde) outer tolerance range 0 b disabled: pdeout = pdein. 1 b enabled: if pdein > abs(7/16) bit then pdeout = 0 else pdeout = pdein. reset: 1 h phden0 4 w phase detector error (pde) inner tolerance range 0 b disabled: pdeout = pdein. 1 b enabled: if pdein < abs(1/16) bit then pdeout = 0 else pdeout = pdein. reset: 0 h pval 3:2 w p value. the pval is the p value of the clock-recovery pi loop- filter. the phase- detector output error will be multiplied with the set value. 00 b 1/1 phase detector error 01 b 1/2 phase detector error 10 b 1/4 phase detector error 11 b 1/8 phase detector error reset: 1 h psat 1:0 w p value saturation. the saturation of the p-loop-filter path will be set according to the psat value. remark that the internal phase resolution of the phase detector is 1/16 bit. 00 b saturation to 1/16 bit 01 b saturation to 2/16 bit 10 b saturation to 4/16 bit 11 b saturation to 8/16 bit reset: 2 h z 3 ' 6 5 z 3 + ' ( 1 z 3 + ' ( 1 z 3 9 $ / z 3 6 $ 7 TDA5235 appendix register description data sheet 213 v1.0, 2010-02-19 a_cdri offset reset value clock and data recovery configuration register 047 h 65 h field bits type description corsat 7:6 w correlator output value (timing extrapolation unit). the timing extrapolation unit output value will be multiplied with the lfsat value. the timing extrapolation unit measures the data rate error during the runin sequence and sets the i-loop-filter path when the runin length is reached. 00 b 1/4 calculated value 01 b 1/8 calculated value 10 b 1/16 calculated value 11 b 1/32 calculated value reset: 1 h lfsat 5:4 w loop filter saturation. the saturati on of the i-loop-filter path will be set according to the lfsat value.remark that the internal phase resolution of the phase detector is 1/16 bit. 00 b saturation to 1/32 bit 01 b saturation to 1/16 bit 10 b saturation to 2/16 bit 11 b saturation to 4/16 bit reset: 2 h ival 3:2 w i value. the ival is the i value of the clock-recovery pi loop-filter. the phase- detector output error will be multiplied with this set value. 00 b 1/32 phase detector error 01 b 1/64 phase detector error 10 b 1/128 phase detector error 11 b 1/256 phase detector error reset: 1 h z & 2 5 6 $ 7 z / ) 6 $ 7 z , 9 $ / z , 6 $ 7 TDA5235 appendix register description data sheet 214 v1.0, 2010-02-19 clock and data recovery runin configuration register cdr dc chip tolerance register isat 1:0 w i value saturation. the saturation of the i-loop-filter accumulator will be set according to the isat value. remark that the internal phase resolution of the phase detector is 1/16 bit. 00 b saturation to 1/16 bit 01 b saturation to 2/16 bit 10 b saturation to 4/16 bit 11 b saturation to 8/16 bit reset: 1 h a_cdrri offset reset value clock and data recovery runin configuration register 048 h 01 h field bits type description unused 7:3 - unused reset: 00 h drlimen 2 w enable data rate error acceptance limitation. the limits are defined in cdrdrthrp and cdrdrthrn registers. 0 b disabled 1 b enabled reset: 0 h runlen 1:0 w runin length. the runin length is equal to pll-start-value calculation time. this means that the shorter runin length decreases the data rate offset calculation accuracy and symbol synchronization found signal generation stability. note that the runlen have to be changed together with the tsi configuration registers. 00 b 8 chips 01 b 7 chips 10 b 6 chips 11 b 5 chips reset: 1 h field bits type description 8 1 8 6 ( ' z ' 5 / , 0 ( 1 z 5 8 1 / ( 1 TDA5235 appendix register description data sheet 215 v1.0, 2010-02-19 cdr dc bit tolerance register a_cdrtolc offset reset value cdr dc chip tolerance register 049 h 0c h field bits type description unused 7:6 - unused reset: 0 h tolchiph 5:3 w duty cycle tolerance for chip border high level. represents the number of 1/16 bit sample deviation from the ideal chip border where an edge can occur in direction to the following chip border. reset: 1 h tolchipl 2:0 w duty cycle tolerance for chip border low level. represents the number of 1/16 bit sample deviation from the ideal chip border where an edge can occur in direction to the previous chip border. reset: 4 h a_cdrtolb offset reset value cdr dc bit tolerance register 04a h 1e h field bits type description unused 7:6 - unused reset: 0 h tolbith 5:3 w duty cycle tolerance for bit border high level. represents the number of 1/16 bit sample deviation from the ideal bit border where an edge can occur in direction to the following bit border. reset: 3 h tolbitl 2:0 w duty cycle tolerance for bit border low level. represents the number of 1/16 bit sample deviation from the ideal bit border where an edge can occur in direction to the previous bit border. reset: 6 h 8 1 8 6 ( ' z 7 2 / & + , 3 + z 7 2 / & + , 3 / 8 1 8 6 ( ' z 7 2 / % , 7 + z 7 2 / % , 7 / TDA5235 appendix register description data sheet 216 v1.0, 2010-02-19 timing violation window register slicer configuration register a_tvwin offset reset value timing violation window register 04b h 28 h field bits type description tvwin 7:0 w timing violati on window length. defines the maximal number of 1/16 data samples without detected edge which will be tolerated by cdr with no loss of symbol synchronization 28h: 40/16 bit ((8 + 16 *cv + 8)*1.25) ffh: 255/16 bit note: in tsigap mode the value must be higher. reset: 28 h a_slccfg offset reset value slicer configuration register 04c h 90 h field bits type description slccfg 7:0 w data slicer configuration value 90 h : chip mode eom-cv: for patterns with code violations in data packet and optimized for activated eom code violation criterion (and optional eom data length criterion) value 94 h : chip mode eom-datalength: for patterns with code violations in data packet and optimized for activated eom data length criterion only (eomdatlen) value 95 h : chip mode transparent: when framer is not used, but ch_data / ch_str are used for data processing value 75 h : bit mode: only for patterns without code violations reset: 90 h z 7 9 : , 1 z 6 / & & ) * TDA5235 appendix register description data sheet 217 v1.0, 2010-02-19 tsi detection mode register tsi length register a a_tsimode offset reset value tsi detection mode register 04d h 80 h field bits type description tsigrsyn 7 w tsi gap resync mode (only for tsidetmode=2 h ) 0 b disabled - in this mode the gapval and tsigap values are used, so the overall gap time can be defined in t/16 steps. 1 b enabled - pll resync after tsi gap in this mode the t/2 gap resolution can be set in the 5 msb tsigap register bits. gapval value is not used. prefered in tsi gap mode. reset: 1 h tsiwca 6:3 w wild cards for 4 lsb chips of correlator a if all 4 chips are 0, the whole tsi pattern for correlator a is valid if a chip is 1, the corresponding chip from the tsi pattern is ignored reset: 0 h cphra 2 w code phase readjustment in payload 0 b disabled - code polarity is defined by the tsi pattern 1 b enabled - code phase readjustment in payload reset: 0 h tsidetmod 1:0 w tsi detection mode 00 b 16 bit tsi mode - tsi configuration b and a valid (sequentially), b is valid if a_tsilena=16 (=10 h ) and the a_tsilenb > 0 01 b 8 bit parallel tsi mode - tsi configurations a or b (parallel) 10 b 8 bit tsi gap mode - tsi configurations a and b with gap (sequentially with gap between tsia & tsib) 11 b 8 bit extended tsi mode - tsi configurations a or b (parallel with matching information), dependent on found tsi a or b, 0 resp. 1 will be sent as 1st received bit. reset: 0 h a_tsilena offset reset value tsi length register a 04e h 00 h z 7 6 , * 5 6 < 1 z 7 6 , : & $ z & 3 + 5 $ z 7 6 , ' ( 7 0 2 ' TDA5235 appendix register description data sheet 218 v1.0, 2010-02-19 tsi length register b tsi gap length register field bits type description unused 7:5 - unused reset: 0 h tsilena 4:0 w tsi a length (in chips): (11 h up to 1f h not used) min: 01 = 1 chip; be aware that such small values makes it impossible to find the right phase of the pattern in the data stream and therefore wrong data and code violations can be generated. max: 10h = 16 chips = 8 bit reset: 00 h a_tsilenb offset reset value tsi length register b 04f h 00 h field bits type description unused 7:5 - unused reset: 0 h tsilenb 4:0 w tsi b length (in chips): (11 h up to 1f h not used) min: for 16 bit tsi mode: min: 00h = 0 chip (see also a_tsilena) for all other tsi modes: min: 01h = 1 chip (see also a_tsilena) max: 10h = 16 chips = 8 bit reset: 00 h 8 1 8 6 ( ' z 7 6 , / ( 1 $ 8 1 8 6 ( ' z 7 6 , / ( 1 % TDA5235 appendix register description data sheet 219 v1.0, 2010-02-19 tsi pattern data reference a register 0 tsi pattern data reference a register 1 a_tsigap offset reset value tsi gap length register 050 h 00 h field bits type description tsigap 7:3 w tsi gap (t/2 bit resolution) 1fh: 15 1/2 bit gap 00h: 0 bit gap tsigap is used to lock the pll after tsi a is found, if the tsi detection mode 10b is selected. reset: 00 h gapval 2:0 w tsi gap (t/16 bit resolution) 111b: 7/16 bit gap 000b: 0 bit gap gapval is used to correct the dco phase after tsigap time, if a_tsimode.tsigrsyn is disabled reset: 0 h a_tsipta0 offset reset value tsi pattern data reference a register 0 051 h 00 h field bits type description tsipta0 7:0 w data pattern for tsi comparison: bit 7...bit 0(lsb) (in chips) reset: 00 h a_tsipta1 offset reset value tsi pattern data reference a register 1 052 h 00 h z 7 6 , * $ 3 z * $ 3 9 $ / z 7 6 , 3 7 $ TDA5235 appendix register description data sheet 220 v1.0, 2010-02-19 tsi pattern data reference b register 0 tsi pattern data reference b register 1 end of message control register field bits type description tsipta1 7:0 w data pattern for tsi comparison: bit 15(msb)...bit 8 (in chips) reset: 00 h a_tsiptb0 offset reset value tsi pattern data reference b register 0 053 h 00 h field bits type description tsiptb0 7:0 w data pattern for tsi comparison: bit 7...bit 0(lsb) (in chips) reset: 00 h a_tsiptb1 offset reset value tsi pattern data reference b register 1 054 h 00 h field bits type description tsiptb1 7:0 w data pattern for tsi comparison: bit 15(msb)...bit 8 (in chips) reset: 00 h z 7 6 , 3 7 $ z 7 6 , 3 7 % z 7 6 , 3 7 % TDA5235 appendix register description data sheet 221 v1.0, 2010-02-19 eom data length limit register a_eomc offset reset value end of message control register 055 h 05 h field bits type description unused 7:4 - unused reset: 0 h eomsylo 2 w eom by sync loss 0 b disabled 1 b enabled reset: 1 h eomcv 1 w eom by code violation 0 b disabled 1 b enabled reset: 0 h eomdatlen 0 w eom by data length 0 b disabled 1 b enabled reset: 1 h a_eomdlen offset reset value eom data length limit register 056 h 00 h 8 1 8 6 ( ' 5 h v z ( 2 0 6 < / 2 z ( 2 0 & 9 z ( 2 0 ' $ 7 / ( 1 z ' $ 7 / ( 1 TDA5235 appendix register description data sheet 222 v1.0, 2010-02-19 eom data length limit parallel mode register channel configuration register field bits type description datlen 7:0 w length of data field in telegram, only valid when eom criterion is eomdatlen counting of number of payload bits starts after the last tsi bit. eom will be generated after the last payload bit. in 8-bit extended tsi mode, the value must be the payload length + 1, because of the additional bit inserted (matching information). min: 00h = 256 payload bits reg. value 01h = 1 payload bit max: ffh = 255 payload bits reset: 00 h a_eomdlenp offset reset value eom data length limit parallel mode register 057 h 00 h field bits type description datlenp 7:0 w length of data field in telegram in parallel mode for tsi pattern b, only valid when eom criterion is eomdatlen counting of number of payload bits starts after the last tsi bit. eom will be generated after the last payload bit. in 8-bit extended tsi mode, the value must be the payload length + 1, because of the additional bit inserted (matching information). min: 00h = 256 payload bits reg. value 01h = 1 payload bit max: ffh = 255 payload bits reset: 00 h a_chcfg offset reset value channel configuration register 058 h 04 h z ' $ 7 / ( 1 3 TDA5235 appendix register description data sheet 223 v1.0, 2010-02-19 pll mmd integer value register channel 1 field bits type description unused 7 - unused reset: 0 h extproc 6:5 w external data processing 00 b no deactivation of functional blocks 01 b chip data (rx mode: tmcds) - no framing - fsync, mid and eom interrupts disabled - only totim_sync is active - random, equal and pattern wu are disabled (mapped to sync) 10 b data + data mf (rx mode: tmmf, tmrds) - no framing - fsync, mid and eom interrupts disabled - all totims are inactive - only wu on rssi (level criterion) possible 11 b not used reset: 0 h eom2spm 4 w continue with self polling mode after eom detected in run mode self polling 0 b disabled - stay in run mode self polling (next payload frame is expected) 1 b enabled - leave run mode self polling after eom reset: 0 h unused 3 w unused reset: 0 h noc 2 w number of channels (run mode slave / self polling mode - run mode self polling) 0 b channel 1 / channel 1 1 b channel 1 / channel 1 reset: 1 h mt 1:0 w modulation type (run mode slave / self polling mode - run mode self polling) 00 b ask / ask - ask 01 b fsk / fsk - fsk 10 b ask / fsk - ask 11 b fsk / ask - fsk reset: 0 h 8 1 8 6 ( ' z ( ; 7 3 5 2 & z ( 2 0 6 3 0 z 8 1 8 6 ( ' z 1 2 & z 0 7 TDA5235 appendix register description data sheet 224 v1.0, 2010-02-19 pll fractional division ratio register 0 channel 1 pll fractional division ratio register 1 channel 1 a_pllintc1 offset reset value pll mmd integer value register channel 1 059 h 93 h field bits type description bandsel 7:6 w frequency band selection 00 b not used 01 b 915mhz/868mhz 10 b 434mhz 11 b 315mhz reset: 2 h pllintc1 5:0 w sdpll multi modulus divider integer offset value for channel 1 pllint(5:0) = dec2hex(int(f_lo / f_xtal)) reset: 13 h a_pllfrac0c1 offset reset value pll fractional division ratio register 0 channel 1 05a h f3 h field bits type description pllfrac0c1 7:0 w synthesizer channel frequency value (21 bits, bits 7:0), fractional division ratio for channel 1 pllfrac(20:0) = dec2hex(((f_lo / f_xtal) - pllint) * 2^21) reset: f3 h a_pllfrac1c1 offset reset value pll fractional division ratio register 1 channel 1 05b h 07 h z % $ 1 ' 6 ( / z 3 / / , 1 7 & z 3 / / ) 5 $ & & TDA5235 appendix register description data sheet 225 v1.0, 2010-02-19 pll fractional division ratio register 2 channel 1 special function register page register field bits type description pllfrac1c1 7:0 w synthesizer channel frequency value (21 bits, bits 15:8), fractional division ratio for channel 1 pllfrac(20:0) = dec2hex(((f_lo / f_xtal) - pllint) * 2^21) reset: 07 h a_pllfrac2c1 offset reset value pll fractional division ratio register 2 channel 1 05c h 09 h field bits type description unused 7:6 - unused reset: 0 h pllfcompc1 5 w fractional spurii compensation enable for channel 1 0 b disabled 1 b enabled reset: 0 h pllfrac2c1 4:0 w synthesizer channel frequency value (21 bits, bits 20:16), fractional division ratio for channel 1 pllfrac(20:0) = dec2hex(((f_lo / f_xtal) - pllint) * 2^21) reset: 09 h sfrpage offset reset value special function register page register 080 h 00 h z 3 / / ) 5 $ & & 8 1 8 6 ( ' z 3 / / ) & 2 0 3 & z 3 / / ) 5 $ & & TDA5235 appendix register description data sheet 226 v1.0, 2010-02-19 pp0 and pp1 configuration register field bits type description unused 7:1 - unused reset: 00 h sfrpage 0 w selection of register page file (configuration a..d) for spi communication 0 b page 0 (config. a, start address: 000 h ) 1 b page 1 (config. b, start address: 100 h ) reset: 0 h ppcfg0 offset reset value pp0 and pp1 configuration register 081 h 50 h field bits type description pp1cfg 7:4 w port pin 1 output signal selection 0000 b clk_out 0001 b rx_run 0010 b nint 0011 b low 0100 b high 0101 b data 0110 b data_matchfil 0111 b n.u. 1000 b ch_data 1001 b ch_str 1010 b rxd 1011 b rxstr 1100 b n.u. 1101 b n.u. 1110 b n.u. 1111 b n.u. reset: 5 h 8 1 8 6 ( ' z 6 ) 5 3 $ * ( z 3 3 & ) * z 3 3 & ) * TDA5235 appendix register description data sheet 227 v1.0, 2010-02-19 pp2 and pp3 configuration register pp0cfg 3:0 w port pin 0 output signal selection 0000 b clk_out 0001 b rx_run 0010 b nint 0011 b low 0100 b high 0101 b data 0110 b data_matchfil 0111 b n.u. 1000 b ch_data 1001 b ch_str 1010 b rxd 1011 b rxstr 1100 b n.u. 1101 b n.u. 1110 b n.u. 1111 b n.u. reset: 0 h ppcfg1 offset reset value pp2 and pp3 configuration register 082 h 12 h field bits type description z 3 3 & ) * z 3 3 & ) * TDA5235 appendix register description data sheet 228 v1.0, 2010-02-19 ppx port configuration register field bits type description pp3cfg 7:4 w port pin 3 output signal selection 0000 b n.u. 0001 b rx_run 0010 b nint 0011 b low 0100 b high 0101 b data 0110 b data_matchfil 0111 b n.u. 1000 b ch_data 1001 b ch_str 1010 b rxd 1011 b rxstr 1100 b n.u. 1101 b n.u. 1110 b n.u. 1111 b n.u. reset: 1 h pp2cfg 3:0 w port pin 2 output signal selection 0000 b clk_out 0001 b rx_run 0010 b nint 0011 b low 0100 b high 0101 b data 0110 b data_matchfil 0111 b n.u. 1000 b ch_data 1001 b ch_str 1010 b rxd 1011 b rxstr 1100 b n.u. 1101 b n.u. 1110 b n.u. 1111 b n.u. reset: 2 h ppcfg2 offset reset value ppx port configuration register 083 h 00 h TDA5235 appendix register description data sheet 229 v1.0, 2010-02-19 rx run configuration register 0 field bits type description pp3hppen 7 w pp3 high power pad enable 0 b normal 1 b high power reset: 0 h pp2hppen 6 w pp2 high power pad enable 0 b normal 1 b high power reset: 0 h pp1hppen 5 w pp1 high power pad enable 0 b normal 1 b high power reset: 0 h pp0hppen 4 w pp0 high power pad enable 0 b normal 1 b high power reset: 0 h pp3inv 3 w pp3 inversion enable 0 b not inverted 1 b inverted reset: 0 h pp2inv 2 w pp2 inversion enable 0 b not inverted 1 b inverted reset: 0 h pp1inv 1 w pp1 inversion enable 0 b not inverted 1 b inverted reset: 0 h pp0inv 0 w pp0 inversion enable 0 b not inverted 1 b inverted reset: 0 h rxruncfg0 offset reset value rx run configuration register 0 084 h ff h z 3 3 + 3 3 ( 1 z 3 3 + 3 3 ( 1 z 3 3 + 3 3 ( 1 z 3 3 + 3 3 ( 1 z 3 3 , 1 9 z 3 3 , 1 9 z 3 3 , 1 9 z 3 3 , 1 9 TDA5235 appendix register description data sheet 230 v1.0, 2010-02-19 rx run configuration register 1 field bits type description unused 7:6 w unused reset: 3 h rxrunpp1b 5 w rxrun active level on pp1 for configuration b 0 b active low 1 b active high reset: 1 h rxrunpp1a 4 w rxrun active level on pp1 for configuration a 0 b active low 1 b active high reset: 1 h unused 3:2 w unused reset: 3 h rxrunpp0b 1 w rxrun active level on pp0 for configuration b 0 b active low 1 b active high reset: 1 h rxrunpp0a 0 w rxrun active level on pp0 for configuration a 0 b active low 1 b active high reset: 1 h rxruncfg1 offset reset value rx run configuration register 1 085 h ff h field bits type description unused 7:6 w unused reset: 3 h z 8 1 8 6 ( ' z 5 ; 5 8 1 3 3 % z 5 ; 5 8 1 3 3 $ z 8 1 8 6 ( ' z 5 ; 5 8 1 3 3 % z 5 ; 5 8 1 3 3 $ z 8 1 8 6 ( ' z 5 ; 5 8 1 3 3 % z 5 ; 5 8 1 3 3 $ z 8 1 8 6 ( ' z 5 ; 5 8 1 3 3 % z 5 ; 5 8 1 3 3 $ TDA5235 appendix register description data sheet 231 v1.0, 2010-02-19 clock divider register 0 clock divider register 1 rxrunpp3b 5 w rxrun active level on pp3 for configuration b 0 b active low 1 b active high reset: 1 h rxrunpp3a 4 w rxrun active level on pp3 for configuration a 0 b active low 1 b active high reset: 1 h unused 3:2 w unused reset: 3 h rxrunpp2b 1 w rxrun active level on pp2 for configuration b 0 b active low 1 b active high reset: 1 h rxrunpp2a 0 w rxrun active level on pp2 for configuration a 0 b active low 1 b active high reset: 1 h clkout0 offset reset value clock divider register 0 086 h 0b h field bits type description clkout0 7:0 w clock out divider: clkout(19:0) = clkout2(msb) & clkout1 & clkout0(lsb) min: 00002h = clock divided by 2*2 max: fffffh = clock divided by ((2^20)-1)*2 reg. value 00000h = clock divided by (2^20)*2 reset: 0b h clkout1 offset reset value clock divider register 1 087 h 00 h field bits type description z & / . 2 8 7 TDA5235 appendix register description data sheet 232 v1.0, 2010-02-19 clock divider register 2 rf control register field bits type description clkout1 7:0 w clock out divider: clkout(19:0) = clkout2(msb) & clkout1 & clkout0(lsb) min: 00002h = clock divided by 2*2 max: fffffh = clock divided by ((2^20)-1)*2 reg. value 00000h = clock divided by (2^20)*2 reset: 00 h clkout2 offset reset value clock divider register 2 088 h 00 h field bits type description unused 7:4 - unused reset: 0 h clkout2 3:0 w clock out divider: clkout(19:0) = clkout2(msb) & clkout1 & clkout0(lsb) min: 00002h = clock divided by 2*2 max: fffffh = clock divided by ((2^20)-1)*2 reg. value 00000h = clock divided by (2^20)*2 reset: 0 h rfc offset reset value rf control register 089 h 07 h z & / . 2 8 7 8 1 8 6 ( ' z & / . 2 8 7 TDA5235 appendix register description data sheet 233 v1.0, 2010-02-19 bpf calibration configuration register 0 field bits type description unused 7:5 - unused reset: 0 h rfoff 4 w switch off rf-path (for rssi trimming) 0 b rf path enabled 1 b rf path disabled reset: 0 h ifatt 3:0 w adjust if attenuation from lna_in to if_out (double-down conversion / single-down conversion) used to trim out external component tolerances. 0000 b 0 db / n.u. 0001 b 0.8 db / n.u. 0010 b 1.6 db / n.u. 0011 b 2.4 db / n.u. 0100 b 3.2 db / 0 db 0101 b 4.0 db / 0.8 db 0110 b 4.8 db / 1.6 db 0111 b 5.6 db / 2.4 db 1000 b 6.4 db / 3.2 db 1001 b 7.2 db / 4.0 db 1010 b 8.0 db / 4.8 db 1011 b 8.8 db / n.u. 1100 b 9.6 db / n.u. 1101 b 10.4 db / n.u. 1110 b 11.2 db / n.u. 1111 b 12.0 db / n.u. reset: 7 h bpfcalcfg0 offset reset value bpf calibration configuration register 0 08a h 07 h 8 1 8 6 ( ' z 5 ) 2 ) ) z , ) $ 7 7 8 1 8 6 ( ' 5 h v z % 3 ) & $ / 6 7 TDA5235 appendix register description data sheet 234 v1.0, 2010-02-19 bpf calibration configuration register 1 xtal coarse calibration register field bits type description unused 7:5 - unused reset: 0 h bpfcalst 3:0 w bpf calibration time (use default = 07 h ) min: 0h= txtal * 80 * 7 * (0 + 4) max: fh= txtal * 80 * 7 * (15 + 4) reset: 7 h bpfcalcfg1 offset reset value bpf calibration configuration register 1 08b h 04 h field bits type description unused 7:6 - unused reset: 0 h bpfcalbw 5:0 - band pass filter bandwidth selection during calibration 04 h - 50 khz (=default) 0d h - 80 khz 16 h - 125 khz 1f h - 200 khz 27 h - 300 khz reset: 04 h xtalcal0 offset reset value xtal coarse calibration register 08c h 10 h 8 1 8 6 ( ' % 3 ) & $ / % : 8 1 8 6 ( ' z ; 7 $ / 6 : & TDA5235 appendix register description data sheet 235 v1.0, 2010-02-19 xtal fine calibration register rssi monitor configuration register field bits type description unused 7:5 - unused reset: 0 h xtalswc 4:0 w xtal trim capacitor value min 00h: 0pf value 01h: 1pf max 18h: 24pf higher values than 18h are automatically mapped to 24pf reset: 10 h xtalcal1 offset reset value xtal fine calibration register 08d h 00 h field bits type description unused 7:4 - unused reset: 0 h xtalswf3 3 w connect 500 ff xtal trim capacitor 0 b not connected 1 b connected reset: 0 h xtalswf2 2 w connect 250 ff xtal trim capacitor 0 b not connected 1 b connected reset: 0 h xtalswf1 1 w connect 125 ff xtal trim capacitor 0 b not connected 1 b connected reset: 0 h xtalswf0 0 w connect 62.5 ff xtal trim capacitor 0 b not connected 1 b connected reset: 0 h 8 1 8 6 ( ' z ; 7 $ / 6 : ) z ; 7 $ / 6 : ) z ; 7 $ / 6 : ) z ; 7 $ / 6 : ) TDA5235 appendix register description data sheet 236 v1.0, 2010-02-19 adc input selection register rssi offset register rssimonc offset reset value rssi monitor configuration register 08e h 01 h field bits type description unused 7:3 - unused reset: 00 h rssimonen 0 w enable buffer for rssi pin 0 b disabled 1 b enabled reset: 1 h adcinsel offset reset value adc input selection register 08f h 00 h field bits type description unused 7:3 - unused reset: 00 h adcinsel 2:0 w adc input selection 000 b rssi 001 b temperature 010 b vddd / 2 011 b n.u. 100 b n.u. 101 b n.u. 110 b n.u. 111 b n.u. reset: 0 h 8 1 8 6 ( ' 5 h v z 5 6 6 , 0 2 1 ( 1 8 1 8 6 ( ' z $ ' & , 1 6 ( / TDA5235 appendix register description data sheet 237 v1.0, 2010-02-19 rssi slope register cdr data rate acceptance po sitive threshold register rssioffs offset reset value rssi offset register 090 h 80 h field bits type description rssioffs 7:0 w rssi offset compensation value min: 00h= -256 max: ffh= 254 reset: 80 h rssislope offset reset value rssi slope register 091 h 80 h field bits type description rssislope 7:0 w rssi slope compensation value (multiplication value) multiplication factor = rssislope * 2^-7 min: 00h= 0.0 max: ffh= 1.992 reset: 80 h cdrdrthrp offset reset value cdr data rate acceptance positive threshold register 092 h 1e h z 5 6 6 , 2 ) ) 6 z 5 6 6 , 6 / 2 3 ( TDA5235 appendix register description data sheet 238 v1.0, 2010-02-19 cdr data rate acceptance negative threshold register interrupt mask register 0 field bits type description cdrdrthrp 7:0 w data rate acceptance positive threshold value this feature can be turned on with *_cdrri.drlimen. higher the value, more percent of the datarate is tolerated. default => 10% reset: 1e h cdrdrthrn offset reset value cdr data rate acceptance negative threshold register 093 h 23 h field bits type description cdrdrthrn 7:0 w data rate acceptance negative threshold value this feature can be turned on with *_cdrri.drlimen. higher the value, more percent of the datarate is tolerated. default => 10% reset: 23 h im0 offset reset value interrupt mask register 0 094 h 00 h z & ' 5 ' 5 7 + 5 3 z & ' 5 ' 5 7 + 5 1 z , 0 ( 2 0 % z , 0 0 , ' ) % z , 0 ) 6 < 1 & % z , 0 : 8 % z , 0 ( 2 0 $ z , 0 0 , ' ) $ z , 0 ) 6 < 1 & $ z , 0 : 8 $ TDA5235 appendix register description data sheet 239 v1.0, 2010-02-19 self polling mode active periods register field bits type description imeomb 7 w mask interrupt on "end of message" for configuration b 0 b interrupt enabled 1 b interrupt disabled reset: 0 h immidfb 6 w mask interrupt on "message id found" for configuration b 0 b interrupt enabled 1 b interrupt disabled reset: 0 h imfsyncb 5 w mask interrupt on "frame sync" for configuration b 0 b interrupt enabled 1 b interrupt disabled reset: 0 h imwub 4 w mask interrupt on "wake-up" for configuration b 0 b interrupt enabled 1 b interrupt disabled reset: 0 h imeoma 3 w mask interrupt on "end of message" for configuration a 0 b interrupt enabled 1 b interrupt disabled reset: 0 h immidfa 2 w mask interrupt on "message id found" for configuration a 0 b interrupt enabled 1 b interrupt disabled reset: 0 h imfsynca 1 w mask interrupt on "frame sync" for configuration a 0 b interrupt enabled 1 b interrupt disabled reset: 0 h imwua 0 w mask interrupt on "wake-up" for configuration a 0 b interrupt enabled 1 b interrupt disabled reset: 0 h spmap offset reset value self polling mode active periods register 096 h 01 h 8 1 8 6 ( ' z 6 3 0 $ 3 TDA5235 appendix register description data sheet 240 v1.0, 2010-02-19 self polling mode idle periods register self polling mode control register field bits type description unused 7:5 - unused reset: 0 h spmap 4:0 w self polling mode active periods value min: 01h = 1 (master) period max: 1fh = 31(master) periods reg. value 00h = 32 (master) periods reset: 01 h spmip offset reset value self polling mode idle periods register 097 h 01 h field bits type description spmip 7:0 w self polling mode idle periods value min: 01h = 1 (master) period max: ffh = 255 (master) periods reg. value 00h = 256 (master) periods reset: 01 h spmc offset reset value self polling mode control register 098 h 00 h field bits type description unused 7:3 - unused reset: 00 h z 6 3 0 , 3 8 1 8 6 ( ' z 6 3 0 $ , ( 1 z 6 3 0 6 ( / TDA5235 appendix register description data sheet 241 v1.0, 2010-02-19 self polling mode reference timer register self polling mode off time register 0 spmaien 2 w self polling mode active idle enable 0 b disabled 1 b enabled reset: 0 h spmsel 1:0 w self polling mode selection 00 b constant on/off (coo) 01 b fast fall back to sleep (ffb) 10 b mixed mode (mm, combination of const on/off and fast fall back to sleep for different configurations: coo, ffb, ffb, ffb) 11 b permanent wake up search (pwus) reset: 0 h spmrt offset reset value self polling mode reference timer register 099 h 01 h field bits type description spmrt 7:0 w self polling mode reference timer value the output of this timer is used as input for the on/off timer incoming periodic time = 64 / fsys output periodic time = trt = (64 * spmrt) / fsys min: 01h = (64*1) / fsys max: 00h = (64 * 256) / fsys reset: 01 h spmofft0 offset reset value self polling mode off time register 0 09a h 01 h field bits type description z 6 3 0 5 7 z 6 3 0 2 ) ) 7 TDA5235 appendix register description data sheet 242 v1.0, 2010-02-19 self polling mode off time register 1 self polling mode on time config a register 0 field bits type description spmofft0 7:0 w self polling mode off time value: spmofft(13:0) = spmofft1(msb) & spmofft0(lsb) off -time = trt * spmofft min: 0001h = 1 * trt reg.value 3fffh = 16383 * trt max: 0000h = 16384 * trt reset: 01 h spmofft1 offset reset value self polling mode off time register 1 09b h 00 h field bits type description unused 7:6 - unused reset: 0 h spmofft1 5:0 w self polling mode off time value: spmofft(13:0) = spmofft1(msb) & spmofft0(lsb) off -time = trt * spmofft min: 0001h = 1 * trt reg.value 3fffh = 16383 * trt max: 0000h = 16384 * trt reset: 00 h spmonta0 offset reset value self polling mode on time config a register 0 09c h 01 h 8 1 8 6 ( ' z 6 3 0 2 ) ) 7 z 6 3 0 2 1 7 $ TDA5235 appendix register description data sheet 243 v1.0, 2010-02-19 self polling mode on time config a register 1 self polling mode on time config b register 0 field bits type description spmonta0 7:0 w set value self polling mode on time: spmonta(13:0) = spmonta1(msb) & spmonta0(lsb) on-time = trt *spmonta min: 0001h = 1*trt reg.value: 3fffh = 16383*trt max: 0000h = 16384*trt reset: 01 h spmonta1 offset reset value self polling mode on time config a register 1 09d h 00 h field bits type description unused 7:6 - unused reset: 0 h spmonta1 5:0 w set value self polling mode on time: spmonta(13:0) = spmonta1(msb) & spmonta0(lsb) on-time = trt *spmonta min: 0001h = 1*trt reg.value: 3fffh = 16383*trt max: 0000h = 16384*trt reset: 00 h spmontb0 offset reset value self polling mode on time config b register 0 09e h 01 h 8 1 8 6 ( ' z 6 3 0 2 1 7 $ z 6 3 0 2 1 7 % TDA5235 appendix register description data sheet 244 v1.0, 2010-02-19 self polling mode on time config b register 1 external processing command register field bits type description spmontb0 7:0 w set value self polling mode on time: spmontb(13:0) = spmontb1(msb) & spmontb0(lsb) on-time = trt *spmontb min: 0001h = 1*trt reg.value: 3fffh = 16383*trt max: 0000h = 16384*trt reset: 01 h spmontb1 offset reset value self polling mode on time config b register 1 09f h 00 h field bits type description unused 7:6 - unused reset: 0 h spmontb1 5:0 w set value self polling mode on time: spmontb(13:0) = spmontb1(msb) & spmontb0(lsb) on-time = trt *spmontb min: 0001h = 1*trt reg.value: 3fffh = 16383*trt max: 0000h = 16384*trt reset: 00 h extpcmd offset reset value external processing command register 0a4 h 00 h 8 1 8 6 ( ' z 6 3 0 2 1 7 % 5 h v 8 1 8 6 ( ' z f $ * & 0 $ 1 ) z f $ ) & 0 $ 1 ) z f ( ; 7 7 2 7 , 0 z f ( ; 7 ( 2 0 TDA5235 appendix register description data sheet 245 v1.0, 2010-02-19 chip mode control register 1 field bits type description unused 6:4 - unused reset: 0 h agcmanf 3 wc agc manual freeze when *_agcsfcfg.agcfreeze set to spi command, this bit sets the agc to freeze mode 0 b inactive 1 b active reset: 0 h afcmanf 2 wc afc manual freeze when *_afcsfcfg.afcfreeze set to spi command, this bit sets the afc to freeze mode 0 b inactive 1 b active reset: 0 h exttotim 1 wc force totim signal in external data processing mode (*_chcfg.extroc = 1 h or 2 h ) 0 b no external totim signal forced 1 b external totim signal forced reset: 0 h exteom 0 wc force eom signal in external data processing mode (*_chcfg.extroc = 1 h or 2 h ) 0 b no external eom signal forced 1 b external eom signal forced reset: 0 h cmc1 offset reset value chip mode control register 1 0a5 h 04 h field bits type description unused 7:6 - unused reset: 0 h eom2ncfg 5 w continue with next configuration in self polling mode after eom detected in run mode self polling 0 b continue with configuration a in self polling mode 1 b continue with next configuration in self polling mode reset: 0 h 8 1 8 6 ( ' z ( 2 0 1 & ) * z 7 2 7 , 0 1 & + z , 1 , 7 ) , ) 2 z ) 6 , 1 , 7 ) , ) 2 z ) , ) 2 / . z ; 7 $ / + 3 0 6 TDA5235 appendix register description data sheet 246 v1.0, 2010-02-19 chip mode control register 0 totim2nch 4 w continue with next configuration in self polling mode after totim detected in run mode self polling. 0 b continue with configuration a in self polling mode 1 b continue with next configuration in self polling mode reset: 0 h initfifo 3 w initialization of fifo at cycle start this initialization of the fifo can be configured in both run mode slave and self polling mode. in run mode slave this happens at the beginning. in self polling mode the initialization is done after wake up found (switching from self polling mode to run mode self polling). 0 b initialization disabled 1 b initialization enabled reset: 0 h fsinitfifo 2 w initialization of fifo at frame start 0 b initialization disabled 1 b initialization enabled reset: 1 h fifolk 1 w lock data fifo at eom 0 b fifo lock is disabled 1 b fifo lock is enabled at eom. this also locks the digital receive chain at eom until release from fifo lock state. reset: 0 h xtalhpms 0 w xtal high precision mode in sleep mode 0 b disabled 1 b enabled reset: 0 h cmc0 offset reset value chip mode control register 0 0a6 h 10 h field bits type description sdohppen 7 w sdo high power pad enable 0 b normal 1 b high power reset: 0 h field bits type description z 6 ' 2 + 3 3 ( 1 z , 1 , 7 3 / / + 2 / ' z + 2 / ' z & / . 2 8 7 ( 1 z 8 1 8 6 ( ' z 0 & 6 z 6 / 5 ; ( 1 z 0 6 ( / TDA5235 appendix register description data sheet 247 v1.0, 2010-02-19 wakeup peak detector readout register initpllhold 6 w init pll after coming from hold (when new channel programmed). this requires an additional channel hop time before initialization of the digital receiver. 0 b no init of pll 1 b init of pll reset: 0 h hold 5 w holds the chip in the register configuration state (only in run mode slave) 0 b normal operation 1 b jump into the register config state hold reset: 0 h clkouten 4 w clk_out enable 0 b disabled 1 b enable programmable clock output reset: 1 h unused 3 w unused reset: 0 h mcs 2 w multi configuration selection (run mode slave / self polling mode) 0 b config a / config a 1 b config b / config a + b reset: 0 h slrxen 1 w slave receiver enable this bit is only used in operating mode run mode slave / sleep mode 0 b receiver is in sleep mode 1 b receiver is in run mode slave reset: 0 h msel 0 w operating mode selection 0 b run mode slave / sleep mode 1 b self polling mode reset: 0 h rssipwu offset reset value wakeup peak detector readout register 0a7 h 00 h field bits type description 5 6 6 , 3 : 8 TDA5235 appendix register description data sheet 248 v1.0, 2010-02-19 interrupt status register 0 field bits type description rssipwu 7:0 - peak detector level at wakeup set at every wu event and also set at the end of every configuration/channel cycle within a self polling period. cleared at reset only. reset: 00 h is0 offset reset value interrupt status register 0 0a8 h ff h field bits type description eomb 7 rc interrupt request by "end of message" from configuration b (reset event sets all bits to 1) 0 b not detected 1 b detected reset: 1 h midfb 6 rc interrupt request by "message id found" from configuration b (reset event sets all bits to 1) 0 b not detected 1 b detected reset: 1 h fsyncb 5 rc interrupt request by "frame sync" from configuration b (reset event sets all bits to 1) 0 b not detected 1 b detected reset: 1 h wub 4 rc interrupt request by "wake up" from configuration b (reset event sets all bits to 1) 0 b not detected 1 b detected reset: 1 h eoma 3 rc interrupt request by "end of message" from configuration a (reset event sets all bits to 1) 0 b not detected 1 b detected reset: 1 h u f ( 2 0 % u f 0 , ' ) % u f ) 6 < 1 & % u f : 8 % u f ( 2 0 $ u f 0 , ' ) $ u f ) 6 < 1 & $ u f : 8 $ TDA5235 appendix register description data sheet 249 v1.0, 2010-02-19 rf pll actual channel and configuration register midfa 2 rc interrupt request by "message id found" from configuration a (reset event sets all bits to 1) 0 b not detected 1 b detected reset: 1 h fsynca 1 rc interrupt request by "frame sync" from configuration a (reset event sets all bits to 1) 0 b not detected 1 b detected reset: 1 h wua 0 rc interrupt request by "wake up" from configuration a (reset event sets all bits to 1) 0 b not detected 1 b detected reset: 1 h rfpllacc offset reset value rf pll actual channel and configuration register 0aa h 00 h field bits type description pldlen 7:6 r payload data length stored at tsi detection of the next message, pldlen(9:0) = rfpllacc.pldlen(msb) & pldlen(lsb). cleared with init fifo min. 000h = 0 bits received max. 3ffh = 1023 bits received reset: 0 h unused 5 r unused reset: 0 h rmspacfg 4 r rf pll run mode self polling actual configuration 0 b configuration a 1 b configuration b reset: 0 h unused 3 r unused reset: 0 h field bits type description u 3 / ' / ( 1 u 8 1 8 6 ( ' u 5 0 6 3 $ & ) * u 8 1 8 6 ( ' u 5 0 6 3 $ & u 8 1 8 6 ( ' u 6 3 0 $ & TDA5235 appendix register description data sheet 250 v1.0, 2010-02-19 rssi peak detector readout register rssi payload peak detector readout register rmspac 2 r rf pll run mode self polling actual channel 0 b no valid data in fifo from any channel and configuration 1 b data in fifo belong to channel 1 reset: 0 h unused 1 r unused reset: 0 h spmac 0 r rf pll self polling mode actual channel 0 b no wake up from any channel was actually found 1 b wake up was found from channel 1 reset: 0 h rssiprx offset reset value rssi peak detector readout register 0ab h 00 h field bits type description rssiprx 7:0 rc rssi peak level during receiving tracking is active when digital receiver is enabled set at higher peak levels than stored cleared at reset and spi read out reset: 00 h rssippl offset reset value rssi payload peak detector readout register 0ac h 00 h field bits type description u f 5 6 6 , 3 5 ; u 5 6 6 , 3 3 / TDA5235 appendix register description data sheet 251 v1.0, 2010-02-19 payload data length register adc result high byte register field bits type description rssippl 7:0 r rssi peak level during payload tracking starts after fsync + pkbitpos set at every eom cleared at the reset only reset: 00 h pldlen offset reset value payload data length register 0ad h 00 h field bits type description pldlen 7:0 r payload data length stored at tsi detection of the next message, pldlen(9:0) = rfpllacc.pldlen(msb) & pldlen(lsb). cleared with init fifo min. 000h = 0 bits received max. 3ffh = 1023 bits received reset: 00 h adcresh offset reset value adc result high byte register 0ae h 00 h field bits type description adcresh 7:0 rc adc result value adcres(9:0) = adcresh(7:0) & adcresl(1:0) note: rc for control signal generation only, no clear reset: 00 h u 3 / ' / ( 1 u f $ ' & 5 ( 6 + TDA5235 appendix register description data sheet 252 v1.0, 2010-02-19 adc result low byte register vco autocalibration result readout register afc offset read register adcresl offset reset value adc result low byte register 0af h 00 h field bits type description unused 7:3 - unused reset: 00 h adceoc 2 r adc end of conversion detected 0 b not detected 1 b detected reset: 0 h adcresl 1:0 r adc result value adcres(9:0) = adcresh(7:0) & adcresl(1:0) the 2 lsbs of the adc result are captured when the sfr register adcresh is readout. reset: 0 h vacres offset reset value vco autocalibration result readout register 0b0 h 00 h field bits type description unused 7:5 - unused reset: 0 h vacres 3:0 r vco autocalibration result returns the vco range selected by vco autocalibration reset: 0 h 8 1 8 6 ( ' u $ ' & ( 2 & u $ ' & 5 ( 6 / 8 1 8 6 ( ' 5 h v u 9 $ & 5 ( 6 TDA5235 appendix register description data sheet 253 v1.0, 2010-02-19 agc gain readout register spi address tracer register afcoffset offset reset value afc offset read register 0b1 h 00 h field bits type description afcoffs 7:0 r readout of the frequency offset found by afc (afc loop filter output). value is in signed representation. frequency resolution is 2.68 khz/digit output can be limited by x_afclimit register update rate is 548 khz reset: 00 h agcgainr offset reset value agc gain readout register 0b2 h 00 h field bits type description unused 7:3 - unused reset: 00 h if2gain 2:1 r agc if2 gain readout 00 b 0 db 01 b -15 db 10 b -30 db 11 b n.u. reset: 0 h mix2gain 0 r agc mix2 gain readout 0 b 0 db 1 b -15 db reset: 0 h u $ ) & 2 ) ) 6 8 1 8 6 ( ' u , ) * $ , 1 u 0 , ; * $ , 1 TDA5235 appendix register description data sheet 254 v1.0, 2010-02-19 spi data tracer register spi checksum register spiat offset reset value spi address tracer register 0b3 h 00 h field bits type description spiat 7:0 r spi address tracer, readout of the last address of a sfr register written by spi reset: 00 h spidt offset reset value spi data tracer register 0b4 h 00 h field bits type description spidt 7:0 r spi data tracer, readout of the last written data to a sfr register by spi reset: 00 h spichksum offset reset value spi checksum register 0b5 h 00 h u 6 3 , $ 7 u 6 3 , ' 7 u f 6 3 , & + . 6 8 0 TDA5235 appendix register description data sheet 255 v1.0, 2010-02-19 serial number register 0 serial number register 1 serial number register 2 field bits type description spichksum 7:0 rc spi checksum readout reset: 00 h sn0 offset reset value serial number register 0 0b6 h 00 h field bits type description sn0 7:0 r serial number: sn(31:0) = sn 3(msb) & sn2 & sn1 & sn0(lsb) reset: 00 h sn1 offset reset value serial number register 1 0b7 h 00 h field bits type description sn1 7:0 r serial number: sn(31:0) = sn 3(msb) & sn2 & sn1 & sn0(lsb) reset: 00 h sn2 offset reset value serial number register 2 0b8 h 00 h u 6 1 u 6 1 TDA5235 appendix register description data sheet 256 v1.0, 2010-02-19 serial number register 3 rssi readout register rssi peak memory filter readout register field bits type description sn2 7:0 r serial number: sn(31:0) = sn 3(msb) & sn2 & sn1 & sn0(lsb) reset: 00 h sn3 offset reset value serial number register 3 0b9 h 00 h field bits type description sn3 7:0 r serial number: sn(31:0) = sn 3(msb) & sn2 & sn1 & sn0(lsb) reset: 00 h rssirx offset reset value rssi readout register 0ba h 00 h field bits type description rssirx 7:0 r rssi value after averaging over 4 samples reset: 00 h u 6 1 u 6 1 u 5 6 6 , 5 ; TDA5235 appendix register description data sheet 257 v1.0, 2010-02-19 signal power readout register noise power readout register rssipmf offset reset value rssi peak memory filter readout register 0bb h 00 h field bits type description rssipmf 7:0 - rssi peak memory filter level reset: 00 h spwr offset reset value signal power readout register 0bc h 00 h field bits type description spwr 7:0 r signal power the register contains the actual signal power which should be used to calculate the value of x_sigdet0, x_sigdet1 and x_sigdetlo registers reset: 00 h npwr offset reset value noise power readout register 0bd h 00 h 5 6 6 , 3 0 ) u 6 3 : 5 u 1 3 : 5 TDA5235 appendix register description data sheet 258 v1.0, 2010-02-19 field bits type description npwr 7:0 r fsk noise power the register contains the actual noise power which should be used to calculate the value for the x_ndthres register reset: 00 h www.infineon.com published by infineon technologies ag |
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